Design & Implementation of PCI Express BUS Physical layer using VHDL.pdf - International Journal on Recent and Innovation Trends in Computing and

Design & Implementation of PCI Express BUS Physical layer using VHDL.pdf

This preview shows page 1 - 2 out of 4 pages.

International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169 Volume: 2 Issue: 7 1883 1886 _______________________________________________________________________________________________ 1883 IJRITCC | July 2014, Available @ _______________________________________________________________________________________ Design & Implementation of PCI Express BUS Physical layer using VHDL Ankita R. Tembhare Research Scholar JDCOEM Nagpur University, Maharashtra, India [email protected] Dr.Pramod B. Patil Principal JDCOEM, Nagpur University, Maharashtra, India [email protected] Abstract: - This paper presents the proposal of the implementation of the Physical Link Layer of PCI-Express, as is defined in PCI Express1.0.The architecture presented here contains the transmission and receiver modules which ensure the reliably conveying of the Transaction Layer Packet (TLP) and Data link Layer Packet(DLLP) between two components using the PCI-Express protocol. This paper explains how the implementation makes the reliably conveying ,through the addition of a start and end bits to each data coming in from the Transaction and Data link Layer in the transmit side, and how the packets are processed in receiver side. The whole architecture will be implemented on Altera or similar FPGAs to indicate that this architecture is a feasible approach. PCI Express bus architecture will be implemented on VHDL platform Keywords - PCI Express, TLP, DLLP, FPGA, Xilinx, vertex. __________________________________________________*****_________________________________________________ 1. Introduction: PCI Express is the third generation high performance I/O bus used to interconnect peripheral devices in applications such as computing and communication platform. PCI Express is a high speed serial computer bus standard designed to replace the older PCI, PCI-X bus standard. Most state of the art PCI have new bus called PCI Express. It is a 3 rd generation high performance I/O Bus used to interconnect peripheral devices in applications such as mobile,desktop, workstations ,server, a serial, point to point type interconnect for communication platforms. PCI Express technology implements a serial interconnect between two devices result in fewer pins for device package, which reduces the PCI Express chip ,board design cost and design complexity. PCI Express implement switch based technology to interconnect a large number of devices. Communication over the serial interconnect is accomplished using a packet based communication protocol. Physical layer link should be configured varing from 1-32 lanes ,with each lane carring a maximum data rate of 2.5GB/s. Since the first PC, launched in 1981, the computer has had expansion slots where you can install additional cards to add apabilities not available on the motherboard of the computer. Currently, the most common type of expansion slot available is called PCI Express PCI stands for Peripheral Component Interconnect. PCI Express has been launched by Intel in 2004 to replace the PCI extension bus. This bus is used as a communication lane to transmit signals and data from your computer system to peripheral devices attached to your computer. Hence, PCI Express, also known as 3GIO, is a computer expansion card interface, will transmit data along four point-to-point serial data lanes.
Image of page 1
Image of page 2

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture