SystemVerilog [Verification] Data-Types
Overview
What is SystemVerilog?
•
S
ystemVerilog as an Extension of Verilog
Data-Types
•
4-State Data Types
•
logic
•
2-State Data Types
•
s
hortint
,
int
longint
•
b
yte, bit
•
A
rrays
•
F
ixed Size Arrays
•
for
and
foreach
loop (array initialization)
•
P
acked Arrays
•
D
ynamic Arrays
•
Q
ueues
•
A
ssociative Arrays
•
P
ackages
•
U
ser-Defined data-types
•
C
asting of data-types
•
S
trings
Advanced Hardware Design & Verification
SystemVerilog
[email protected]
1
S
ystemVerilog is a hardware description and Verification language (HDVL)
SystemVerilog [Verification] Data-Types
What is SystemVerilog
Advanced Hardware Design & Verification
SystemVerilog
[email protected]
2
SystemVerilog
Coverage support
Narrow gap b/w design & verification engineer
Constrained Randomization
Easy c model integration
OOP support
New data types ie,logic
Assertions
S
ystemVerilog is an extensive set of enhancements to IEEE 1364 Verilog-2001 standards
I
t has features inherited from Verilog HDL,VHDL,C,C++
A
dds extended features to Verilog
I
t supports all features of Verilog plus add on features
S
ystemVerilog is the superset of Verilog
I
t’s a super
Verilog
A
dditional features of system Verilog will be discussed
SystemVerilog [Verification] Data-Types
What is SystemVerilog
as an Extension of Verilog
Advanced Hardware Design & Verification
SystemVerilog
[email protected]
3
SystemVerilog [Verification] Data-Types
What is SystemVerilog
Summary of new data-types
•
4-State
logic
type
–
similar to
reg
•
2-State
int
,
bit
, byte,
longint
,
shortint
•
bit
user-defined vector
•
byte
8-bit signed integer
•
int
32-bit signed integer
•
shortint
16-bit signed integer
•
longint
64-bit signed integer
•
U
ser-Defined data-types (
typedef
)
•
E
numeration data-types (
enum
)
•
void
as the return type for a function that returns no value
•
package
to declare new types, common tasks and functions.
Initialized to X
Initialized to 0
Advanced Hardware Design & Verification
SystemVerilog
[email protected]
4
S
trict about usage of
“
reg
”
&
“wire”
data type
“logic”
data type can be used so no need
to worry about
“
reg
”
&
“wire”
SystemVerilog [Verification] Data-Types
What is SystemVerilog
Rules
Advanced Hardware Design & Verification
SystemVerilog
[email protected]
5
2 state variable in RTL model may enable
simulators to be more efficient
2 state variable can be used in test
benches, where
“X”
and
“Z”
are not
required
2 state data type added
–
“0”
,
“1”
state
V
ariable types are 4 state
–
“0”
,
“1”,
“X”
and
“Z
”
New Data-Type Rules
Verilog
System Verilog
