Lecture8.pdf - Lecture 8 More SystemVerilog Features Project 3 \u2022 For Project 3 the SHA256 intermediate values are provided in simplified_sha256 \u2022

Lecture8.pdf - Lecture 8 More SystemVerilog Features...

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Lecture 8: More SystemVerilog Features
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2 For Project 3, the SHA256 intermediate values are provided in simplified_sha256.xlsx The wt values at each time t are provided in simplified_sha256_w_values.xlsx See links on course schedule page Project 3
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3 Using $display statements $display("<format>", exp1, exp2, ...); // formatted write to display format indication %b %B binary %c %C character (low 8 bits) %d %D decimal %0d for minimum width field %e %E E format floating point %15.7E %f %F F format floating point %9.7F %g %G G general format floating point %h %H hexadecimal %l %L library binding information %m %M hierarchical name, no expression %o %O octal %s %S string , 8 bits per character %t %T simulation time, expression is $time %u %U unformatted two value data 0 and 1 %v %V net signal strength %z %Z unformatted four value data 0, 1, x, z // $display will automatically insert a newline $write // same as $display except no automatic insertion of newline $monitor // same as $display except only displays if expression changes
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4 Using $display statements escape sequences, quoted characters in strings \n newline \t tab \\ backslash \" quote \ddd character by octal code of 1-3 digits (0 d 7) %% percent any other characters between the quotes are displayed the expressions are taken in order of the format indication ,, in the expression list inserts one space in the output
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5 Using $display statements function logic [255:0] sha256_op(input logic [31:0] a, b, c, d, e, f, g, h, w, k); logic [31:0] S1, S0, ch, maj, t1, t2; // internal signals begin S1 = rightrotate(e, 6) ^ rightrotate(e, 11) ^ rightrotate(e, 25); ch = (e & f) ^ ((~e) & g); t1 = ch + S1 + h + k + w; S0 = rightrotate(a, 2) ^ rightrotate(a, 13) ^ rightrotate(a, 22); maj = (a & b) ^ (a & c) ^ (b & c); t2 = maj + S0; // this displays the next values of a, b, c, d, e, f, g, h // just like the spreadsheet $display("%h %h %h %h %h %h %h %h", t1 + t2, a, b, c, d + t1, e, f, g); sha256_op = {t1 + t2, a, b, c, d + t1, e, f, g}; end endfunction always_ff @(...) begin if (!reset_n) begin ... end else begin ... $write("%2d ", t); {a, b, c, d, e, f, g, h} <= sha256_op(a, b, c, d, e, f, g, h, w[15], t); ... end end
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6 Modelsim in Command Line Mode To run Modelsim in command line mode, create a work directory: vlib work You just have to run this command once to create the work directory. To compile a design with testbench, run the following (using for example tb_fibonacci_calculator.sv and fibonacci_calculator.sv ): vlog tb_fibonacci_calculator.sv fibonacci_calculator.sv If there are other SystemVerilog files, include them on this command line a well. To simulate, run the following (again using the fibonacci calculator example): vsim -c -do "run -all" tb_fibonacci_calculator The simulation transcript is also saved in a file named transcript .
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7 Modelsim in Command Line Mode Make sure that the command line shell can find executables vlib , vlog , and vsim by setting the appropriate environment PATH variable. This should normally be set when you install ModelSim. For example, it might be located here: C:\intelFPGA_lite\17.1\modelsim_ase\win32aloem
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1 This lecture provides more ways of using functions Recall that “functions” should only be used to describe “combinational logic”, same as the way combinational logic is described in “always_comb” (combinational always statements) More on Functions
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  • Fall '19
  • SystemVerilog, Don Mills, Stu Sutherland,  VCS

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