CSE320cheat - Consider the following component-level...

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Consider the following component-level diagram of a 4-to-2 priority encoder with a "valid output" signal, where W is the highest priority input signal. +------+ W--> | |-->VALID X--> | | Y--> | |-->F1 Z--> | |-->F0 +------+ When all four of the input signals are deasserted (the logical value zero), the "VALID" signal is deasserted and the other two output signals are both irrelevant. Otherwise, the "VALID" signal is asserted (the logical value one) and the priority encoder performs its normal encoding operation. a) Describe the functionality of this priority encoder using a truth table or a characteristic table. W X Y Z | Valid F1 F0 -----------------+------------ 0 0 0 0 | 0 X X 0 0 0 1 | 1 0 0 0 0 1 X | 1 0 1 0 1 X X | 1 1 0 1 X X X | 1 1 1 b) Give a gate-level diagram of this priority encoder. A correct response would include a circuit diagram for all three functions, based on the Boolean expressions: Valid = W+ X + Y + Z F1 = W + W’X F0 = W + W’X’Y Consider the following component-level diagram of a three-bit sequencer which generates the outputs 001, 010, 100, 001, 010, 100, and so on. +------+ INIT----->| |-->Q2 CLOCK->| |-->Q1 LOAD--->| |-->Q0 +------+ The three "Q" output signals always reflect the current contents of the sequencer. When the asynchronous "INIT" signal is asserted, the sequencer is initialized (the "Q0" output signal is asserted, while the "Q1" and "Q2" output signals are deasserted). When the "LOAD" signal and the "CLOCK" signal are both asserted, the sequencer performs its shift operation. Draw a gate-level diagram of this sequencer. You may assume the existence of gates from the set {NOT, AND, OR} and D flip-flops (you do not need to show the "insides" of those gates or flip-flops). Also, you may assume that the flip-flops have
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This note was uploaded on 03/31/2008 for the course CSE 320 taught by Professor M.mccullen during the Spring '08 term at Michigan State University.

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CSE320cheat - Consider the following component-level...

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