Fall03-prerequisite quiz - 1 University of California,...

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Unformatted text preview: 1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 2003 John Kubiatowicz Prerequisite Quiz September 3, 2003 CS252 Computer Architecture and Engineering This prerequisite quiz will be used in determining class admissions. Good Luck! Your Name: SID Number: Discussion Section: 1 2 3 Total 2 [ This page left for π ] 3.1415926535897932384626433832795028841971693993751058209749445923078164062862 3 Problem 1: Memory Hierarchy Problem 1a: Assume that we have a 32-bit processor (with 32-bit words) and that this processor is byte-addressed (i.e. addresses specify bytes). Suppose that it has a 512-byte cache that is two- way set-associative, has 4-word cache lines, and uses LRU replacement. Split the 32-bit address into “tag”, “index”, and “cache-line offset” pieces. Which address bits comprise each piece? tag: index: cache-line offset: 3—0 (we’ll give you this one). Problem 1b: How many sets does this cache have? Explain. Problem 1c: Draw a block diagram for this cache. Show a 32-bit address coming into the diagram and a 32-bit data result and “Hit” signal coming out. Include, all of the comparators in the system and any muxes as well. Include the data storage memories (indexed by the “Index”),...
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This homework help was uploaded on 01/29/2008 for the course CS 252 taught by Professor Kubiatowicz during the Fall '07 term at University of California, Berkeley.

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Fall03-prerequisite quiz - 1 University of California,...

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