Fall03-quiz1 - University of California Berkeley College of...

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 2003 John Kubiatowicz Midterm I October 20, 2003 CS252 Graduate Computer Architecture SOLUTIONS Your Name: SID Number: Problem Possible Score 1 25 2 25 3 30 4 20 Total 100
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2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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3 Question #1: Short Answer 1a) What are precise exceptions and why are they desirable? Give 3 reasons. Precise Exceptions are interruptions in the flow of instructions with a single identifiable instruction such that (1) all instructions prior to that instruction have committed their state and (2) neither the identified instruction nor any following instructions have altered the state of the machine. They are desirable because they make resuming from exceptions much simpler. They also make it much simpler to identify the source of the exception (which instruction caused the problem). Finally, they make the exception handling code independent of the underlying architecture. We will take any other reasonable advantages… 1b) What hardware structure can be used to support branch prediction, data prediction, and precise exceptions in an out-of-order processor? Explain what this structure is (including what information it holds) and how it is used with implicit register renaming to recover from a bad prediction or exception. The Reorder Buffer (ROB) supports all of these activities. This structure holds instructions in their original issue order so that they can be committed back in the same order. It holds the instruction itself, tags to indicate which functional unit will produce the result, the final value of the instruction, and various flags to indicate the status of the instruction. Instructions at the head of the ROB (the oldest ones) that are completed can be “committed” by writing their values into the destination registers in the register file. Since values are written back into the register file in order we can recover from a bad prediction or exception simply by discarding the contents of the ROB. 1c) Name all the overheads that occur in an interrupt handler for receiving a network message: There are lost cycles due to flushing the pipeline. There are cycles for disabling interrupts at the beginning and reenabling them at the end. There are cycles for saving and restoring registers. There are cycles for changing the interrupt level. There are cycles for manipulating the interrupt registers on the network controller. Everything else could be considered the body of the interrupt handler. 1d) Name two components of a modern superscalar architecture whose delay scales quadratically with the issue-width. There are several such things. The renaming logic, the forwarding logic, and the decode logic fit in this category.
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4 1e) Suppose we start with a basic Tomasulo architecture that includes branch prediction. What changes are required to execute 4 instructions per cycle?
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