Fall03-prerequisite quiz - University of California...

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 2003 John Kubiatowicz Prerequisite Quiz SOLUTIONS September 3, 2003 CS252 Computer Architecture and Engineering This prerequisite quiz will be used in determining class admissions. Good Luck! Your Name: SID Number: Discussion Section: 1 2 3 Total
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3 Problem 1: Memory Hierarchy Problem 1a: Assume that we have a 32-bit processor (with 32-bit words) and that this processor is byte-addressed (i.e. addresses specify bytes). Suppose that it has a 512-byte cache that is two- way set-associative, has 4-word cache lines, and uses LRU replacement. Split the 32-bit address into “tag”, “index”, and “cache-line offset” pieces. Which address bits comprise each piece? tag: bits 31—8 index: bits 7—4 cache-line offset: bits 3—0 (we’ll give you this one). Problem 1b: How many sets does this cache have? Explain. Since the index is 4 bits, there are 2 4 =16 sets. Problem 1c: Draw a block diagram for this cache. Show a 32-bit address coming into the diagram and a 32-bit data result and “Hit” signal coming out. Include, all of the comparators in the system and any muxes as well. Include the data storage memories (indexed by the “Index”), the tag matching logic, and any muxes. You can indicate RAM with a simple block, but make sure to label address widths and data widths. Make sure to label the function of various blocks and the width of any buses. Address[7:4] TAG<24bits> DATA<128bits> 0 1 2 3 13 14 15 Valid TAG<24bits> DATA<128bits> 0 1 2 3 13 14 15 Valid =? =? Address[31:8] MUX (2-1) 128 128 1 0 24 24 24 MUX (4-1) 128 Address[3:2] 32 SEL HIT 24
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5 Problem 1d: Below is a series of memory read references set to the cache from part (a). Assume that the cache is initially empty and classify each memory references as a hit or a miss. Identify each miss as either compulsory, conflict, or capacity. One example is shown. Hint: start by splitting the address into components. Show your work.
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