Fall03-quiz1 - University of California, Berkeley College...

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 2003 John Kubiatowicz Midterm I October 20, 2003 CS252 Graduate Computer Architecture Your Name: SID Number: Problem Possible Score 1 25 2 25 3 30 4 20 Total 100
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2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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3 Question #1: Short Answer 1a) What are precise exceptions and why are they desirable? Give 3 reasons. 1b) What hardware structure can be used to support branch prediction, data prediction, and precise exceptions in an out-of-order processor? Explain what this structure is (including what information it holds) and how it is used with implicit register renaming to recover from a bad prediction or exception. 1c) Name all the overheads that occur in an interrupt handler for receiving a network message: 1d) Name two components of a modern superscalar architecture whose delay scales quadratically with the issue-width.
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4 1e) Suppose we start with a basic Tomasulo architecture that includes branch prediction. What changes are required to execute 4 instructions per cycle? 1f) What could prevent the above architecture from sustaining 4 instructions per cycle? How does Simultaneous-Multithreading help? 1g) Most branches in a program are highly biased, i.e. they can be predicted by a simple one- level predictor. What can the compiler do to improve the number of branches that are in this category? 1h) Explain which aspects of register renaming removes WAW and WAR hazards in basic the Tomasulo architecture (different answer for each!):
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5 1i) Why is it important to issue instructions in order? 1j) What is memory disambiguation? Describe the minimal hardware support required to perform conservative memory disambiguation in an out-or-order processor (which means that you never send a load to the memory system unless you know that you should) and list pseudo-code that is followed when dispatching loads and/or stores. 1k) Draw each of these predictors: GAs, PAp, Gshare
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6 Problem #2: In-Order Superscalar Processor Consider a dual-issue, in-order pipeline with one fetch stage, one decode stage, multiple execution stages (which include memory access) and a single write-back stage. Assume that the execution stages are organized into two parallel execution pipelines (call them even and odd ) that support all possible simultaneous combinations of two instructions. Instructions wait in the decode stage until all of their dependencies have been satisfied. Further, since this is an in-order pipeline, new instructions will be forced to wait behind stalled instructions. On each cycle, the decode stage takes zero, one, or two ready instructions from the fetch stage, gathers operands from the register file or the forwarding network, then dispatch them to execution stages. If less than 2 instructions are dispatched on a particular cycle, then “NOPs” are sent to the execution stages. When two instructions are dispatched, the even
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Fall03-quiz1 - University of California, Berkeley College...

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