Sp07-quiz1 - University of California, Berkeley College of...

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2007 John Kubiatowicz Midterm I March 21 st , 2007 CS252 Graduate Computer Architecture Your Name: SID Number: Problem Possible Score 1 16 2 21 3 19 4 20 5 24 Total 100
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2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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3 Question #1: Short Answer [16 pts] Problem 1a[2pts]: What is simultaneous multithreading and why is it useful? Probglem 1b[2pts]: What is a data flow architecture? How would it work? Problem 1c[3pts]: What technological forces have caused Intel, AMD, Sun, and others to start putting multiple processors on a chip? Problem 1d[2pts]: Name two components of a modern superscalar architecture whose delay scales quadratically with the issue-width.
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4 Problem 1e[2pts]: Most branches in a program are highly biased, i.e. they can be predicted by a simple one-level predictor. What can the compiler do to improve the number of branches that are in this category? Problem 1f[3pts]: What is the difference between implicit and explicit register renaming? How are they implemented? Problem 1g[2pts]: Why are Vector processors are more power efficient that superscalar processors when executing applications with a lot of data-level parallelism? Explain.
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5 Problem #2: Superpipelining [21 pts] Suppose that we have single-issue, in-order pipeline with one fetch stage, one decode stage, multiple execution stages (which include memory access) and a singe write-back stage. Assume that it has the following execution latencies (i.e. the number of stages that it takes to compute a value): multf (4 cycles), addf (3 cycles), divf (6 cycles), integer ops (1 cycle). Assume full bypassing and two cycles to perform memory accesses, i.e. loads and stores take a total of 3 cycles to execute (including address computation). Finally, branch conditions are computed by the first execution stage (integer execution unit). Problem 2a[10pts]: Assume that this pipeline consists of a single linear sequence of stages in which later stages serve as no-ops for shorter operations. You should do the following on your diagram: 1. Draw each stage of the pipeline as a box and name each of the stages. Stages may have multiple function: i.e. an execute stage + memory op. You will have a total of 9 stages. 2. Describe what is computed in each stage (e.g. EX 1 : Integer Ops, Address Compute, First stage of …) 3. Show all of the bypass paths (as arrows between stages) . Your goal is to design a pipeline which never stalls unless a value is not ready. Label each of these arrows with the types of instructions that will forward their results along these paths (i.e. use “M” for multf, “D” for divf, “A” for addf, “I” for integer operations, “Ld” for loads ). [Hint: be careful to optimize for information feeding into store instructions!]
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This homework help was uploaded on 01/29/2008 for the course CS 252 taught by Professor Kubiatowicz during the Spring '07 term at University of California, Berkeley.

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Sp07-quiz1 - University of California, Berkeley College of...

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