sp07-quiz1

sp07-quiz1 - 1 University of California, Berkeley College...

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Unformatted text preview: 1 University of California, Berkeley College of Engineering Computer Science Division ⎯ EECS Spring 2007 John Kubiatowicz Midterm I SOLUTIONS March 21 st , 2007 CS252 Graduate Computer Architecture Your Name: SID Number: Problem Possible Score 1 16 2 21 3 19 4 20 5 24 Total 100 2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944 3 Question #1: Short Answer [16 pts] Problem 1a[2pts]: What is simultaneous multithreading and why is it useful? Simultaneous multithreading is a technique that adds multiple threads to a multi-issue, out-of- order processor. Since the instructions of these threads can be interleaved in an arbitrary fashion (and are thus running simultaneously), it is called “simultaneous multithreading.” This technique is useful because it can utilize otherwise idle issue slots in a multi-issue processor. Probglem 1b[2pts]: What is a data flow architecture? How would it work? A data flow architecture is one which attempts to exploit the maximum parallelism available in an algorithm. It provides a hardware execution of the “dataflow” graph. Such architectures typically work by placing operations (instructions) in some sort of physical store such that they are triggered immediately when their operands are available. Completion of a given operation generates data which flows to the operand inputs of dependent operations, thus triggering their execution, etc. Problem 1c[3pts]: What technological forces have caused Intel, AMD, Sun, and others to start putting multiple processors on a chip? Power consumption, limited instruction-level parallelism available in typical applications, memory access time (memory wall) and other issues have caused attempts to improve single- thread performance to stall in 2002. The cost in improving single-thread performance reached a point where it wasn’t worth the resulting gain. Chip manufacturers decided to back off from improving individual single-thread performance and instead start making “multicore” chips. Problem 1d[2pts]: Name two components of a modern superscalar architecture whose delay scales quadratically with the issue-width. Many things scale quadratically with issue width. For instance: 1. The delay in the forwarding network scales quadratically with issue-width. 2. The instruction-issue(wakeup) logic scales quadratically with issue-width 3. Register Rename logic scales quadratically 4 Problem 1e[2pts]: Most branches in a program are highly biased, i.e. they can be predicted by a simple one-level predictor. What can the compiler do to improve the number of branches that are in this category? By factoring the code so that it duplicates branches that depend on other branches (called “node splitting”). By copying these branches into multiple instances, one for each path through the code, the new branches can become highly biased.....
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This note was uploaded on 01/29/2008 for the course CS 252 taught by Professor Kubiatowicz during the Spring '07 term at Berkeley.

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sp07-quiz1 - 1 University of California, Berkeley College...

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