Fall1998-quiz2 - University of California Berkeley College...

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University of California, Berkeley College of Engineering Computer Science Division — EECS Fall 1998 J. D. Kubiatowicz Quiz 2 November 20, 1998 CS252 Graduate Computer Architecture You are allowed to use a calculator and one 8.5” x 11” double-sided page of notes. Show your work on all problems. If you find a problem unclear or underspecified, please ask for clarification of the assumptions. If you make assumptions not listed in the problem, please state them clearly in your solutions. Good luck! Your name: SOLUTION SET SID number: Email address: 1 35 /30 2 35 /35 3 35 /35 Total 105 /100
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2 Question 1: Being Consistent a) List the three conditions sufficient for sequential consistency that were presented in class. Hint: one of these dictates the way in which processors can make requests; the other two deal with write atomicity) The following are the three conditions (taken from Culler & Singh, Parallel Computer Archi- tecture, a Hardware/Software Approach, MKP, 1998, p289): Every processor issues memory operations in program order After a write operation is issued, the issuing process waits for the write to complete before issuing its next operation After a read operation is issued, the issuing process waits for the read to complete, and for the write whose value is being returned by the read to complete, before issuing its next operation. That is, if the write whose value is being returned has been performed with respect to this processor, then the processor should wait until the write has been per- formed with respect to all processors b) Draw a diagram illustrating the conditions of write atomicity for two processors ( hint: this dia- gram appeared several times in class ) In the above diagram, arrows indicate the time during which an operation is in progress (the tail is the start of the operation and the head is the end of the operation). LD(A) LD(B) ST(A) LD(A) LD(A) LD(C) Time P2: P1:
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3 Question 1 (continued) c) Describe how the two conditions for write atomicity are satisfied in the following three cases: 1) a snoopy-cache protocol on an atomic bus The bus is atomic, so only one memory transaction can be outstanding at any time. The bus is shared, so it serializes accesses of different processors. Thus it is impossible for a read (or any memory access, for that matter) on processor j to start until any prior write by pro- cessor i has completed and released the bus. Additionally, since the bus is atomic, the coherence transaction needed to read a cache line into the exclusive/modified state will not return the data until all processors have received and processed invalidate messages. Finally, to meet the first condition of sequential consistency, we assume that the processor issues memory operations in-order, and waits for them to complete ( e.g. , there is no write buffer).
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