Fall1998-quiz1 - University of California Berkeley College...

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University of California, Berkeley College of Engineering Computer Science Division — EECS Fall 1998 J. D. Kubiatowicz Quiz 1 October 7, 1998 CS252 Graduate Computer Architecture You are allowed to use a calculator and one 8.5” x 11” double-sided page of notes. Show your work on all problems. If you find a problem unclear or underspecified, please ask for clarification of the assumptions. If you make assumptions not listed in the problem, please state them clearly in your solutions. Good luck! Your name: SID number: Email address: 1 /20 2 /20 3 /40 4 /20 Total /100
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2 Question 1: Being Precise This problem explores some of the issues involved in supporting precise interrupts in a simple 5- stage DLX-like pipeline. (a) Give a simple definition of precise interrupts/exceptions. (b) Why are precise interrupts/exceptions useful? Give 3 examples. (c) Draw a simple block diagram of a 5-stage DLX pipeline, including bypass paths to the execu- tion unit (ALU). Do not include the sign-extension hardware or the hardware needed to opti- mize conditional branches (as presented in class). Be sure to label the pipeline stages.
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3 Question 1 (continued) (d) Consider the following simple instruction sequence: (1) lw r2, 10(r1) ; instruction 1 (2) add r4, r3, r1 ; instruction 2 (3) sub r5, r1, r10 ; instruction 3 Assume that this sequence completes correctly. Using single letters to represent each pipeline stage (F, D, X, M, W), show the time evolution of this sequence (lining up the phases of each instruction): (e) Now assume the following exceptions occur: instruction 1 gets a data TLB fault; instruction 2 gets an overflow; and instruction 3 causes an instruction TLB fault. Produce a diagram as in part (d), with the faulting stages labeled. (f) Which exception happens first in time ? (g) Which exception must be taken in order to have a precise exception?
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4 Question 1 (continued) (h) What sort of hardware support would be necessary to reorder the exceptions so as to get pre- cise interrupts in the 5-stage pipeline (that is, so that the exception identified in part (g) would happen instead of the exception in part (f))?
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