Fall2000-prerequisite quiz

Fall2000-prerequisite quiz - 1 University of California,...

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Unformatted text preview: 1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 2000 John Kubiatowicz Prerequisite Quiz September 6, 2000 CS252 Computer Architecture and Engineering This prerequisite quiz will be used in determining class admissions. Good Luck! Your Name: SID Number: Discussion Section: 1 2 3 Total 2 1) Assume that we have a 64-bit processor with 64-bit words, and that this processor is byte-addressed (i.e. addresses specify bytes). Now, suppose that this processor has a 48-word, three-way, set- associative cache (LRU replacement) with 2-word cache lines. a) Split the 32-bit address into tag, index, and cache-line offset pieces. One is given: tag: index: cache-line offset: bits 3 0 b) Assume that the processor makes the following byte accesses. Label each reference address as a Hit (H) or a Miss (M). Also, identify each cache miss as a compulsory, conflict, or capacity miss. Blank working space is available on the next page. Byte Address Hit/Miss? Miss Type 38(0x026) 172(0x0AC) 144(0x090) 85(0x055) 424(0x1A8) 111(0x06F) 174(0x0AE) 551(0x227) 446(0x1BE) 32(0x020) 428(0x1AC) 544(0x220) 96(0x060) 170(0x0AA) c) Calculate the cache hit rate (you can leave as a fraction). 3 [ This page left for scratch ] 4 2) This problem involves pipeline hazards. Figure 1 shows a simple 5-stage pipeline....
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Fall2000-prerequisite quiz - 1 University of California,...

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