Fall2000-prerequisite quiz - University of California...

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 2000 John Kubiatowicz Prerequisite Quiz SOLUTIONS September 6, 2000 CS252 Computer Architecture and Engineering This prerequisite quiz will be used in determining class admissions. Good Luck! Your Name: SID Number: Discussion Section: 1 2 3 Total
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2 1) Assume that we have a 64-bit processor with 64-bit words, and that this processor is byte-addressed (i.e. addresses specify bytes). Now, suppose that this processor has a 48-word, three-way, set- associative cache (LRU replacement) with 2-word cache lines. a) Split the 32-bit address into “tag”, “index”, and “cache-line offset” pieces. One is given: tag: 63 – 7 index: 6 – 4 cache-line offset: bits 3 – 0 b) Assume that the processor makes the following byte accesses. Label each reference address as a Hit (H) or a Miss (M). Also, identify each cache miss as a compulsory, conflict, or capacity miss. Blank working space is available on the next page. Byte Address Hit/Miss? Miss Type 38(0x026) Miss Compulsory 172(0x0AC) Miss Compulsory 144(0x090) Miss Compulsory 85(0x055) Miss Compulsory 424(0x1A8) Miss Compulsory 111(0x06F) Miss Compulsory 174(0x0AE) Hit 551(0x227) Miss Compulsory 446(0x1BE) Miss Compulsory 32(0x020) Miss Conflict 428(0x1AC) Miss Conflict 544(0x220) Hit 96(0x060) Hit 170(0x0AA) Miss Conflict c) Calculate the cache hit rate (you can leave as a fraction). Hit rate = 3/14
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4 2) This problem involves pipeline hazards. Figure 1 shows a simple 5-stage pipeline. a) What is a branch delay-slot? Is it a feature of the instruction set or of a particular implementation (careful)? A branch delay slot is one or more instructions after a branch which are always executed, regardless of the outcome of the branch (they are logically before the branch). This is a feature of the instruction set because it is programmer-visible (i.e. if you ignore the presence of a branch delay slot, you will get an incorrect program). b) Is the above processor optimized for one or more branch delay slots? If so, how many? The above processor is optimized for one branch delay slot, since the branch decision is made in the decode stage, meaning that the instruction after the branch will always be fetched before the decision can be made We might as well always execute this instruction instead of wasting fetch bandwidth.
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