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Fall99-quiz1 solutions

Computer Architecture: A Quantitative Approach, 4th Edition

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I SOLUTIONS October 13, 1999 CS252 Graduate Computer Architecture Your Name: SID Number: Discussion Section: Problem Possible Score 12 0 2 0 22 0 2 0 33 5 3 5 42 5 2 5 Total 100 100
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2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974945
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3 Question #1: Short Answer 1a) Give a simple definition of precise interrupts/exceptions: An interrupt / exception is precise if the instruction that cause the exception (or during which an interrupt occurred) and all the younger instructions have left no architecturally visible effects (other than in exception registers) and all the older instructions have completed. 1b) Explain how the presence of delayed branches complicates the description of a precise exception point (think about information that the operating system needs to continue execution after an exception)? If an instruction in the shadow of a branch (in a branch delay slot) causes an exception, it is not sufficient to return execution after handling the exception to the pc of the offending instruction because the previous branch has altered the control flow after the instruction. 1c) The Alpha 21064 (first version of the Alpha processor) supported precise exceptions for virtual memory but not for floating point operations. What sort of argument might be used to justify this complicated combination of behaviors? In VM exceptions, recovery is absolutely necessary (without which VM would not work). However, typically threads that cause FP exceptions are terminated, and thus it is not necessary for FP exceptions to be handled in a precise manner. VM exceptions tend to occur more frequently than FP exceptions. FP exception handlers can afford to make the exception precise in software if necessary. 1d) Explain the relationship between support for precise exceptions and support for branch prediction. What hardware structure supports both of these mechanisms in a modern out-of- order pipeline? Handling branch mispredictions and exceptions in a precise manner require younger speculative instructions to be rolled back. The re-order buffer supports both mechanisms.
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5 1e) When is it better to handle events via interrupts rather than polling? How about the reverse? Be specific. In systems where the variance in time between asynchronous events is high, polling can hurt performance and so interrupts are a better choice. In systems where events occur at predictable times (such as communication in scientific hand tuned code), polling can be more effective. 1f) Name 3 different things that people try to predict in modern processors: Branch direction, branch presence, jump targets, load/store dependencies, load values 1g) Why is branch prediction desirable?
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Fall99-quiz1 solutions - University of California Berkeley...

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