Fall1998-quiz1 - University of California Berkeley College...

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University of California, Berkeley College of Engineering Computer Science Division — EECS Fall 1998 J. D. Kubiatowicz Quiz 1 October 7, 1998 CS252 Graduate Computer Architecture You are allowed to use a calculator and one 8.5” x 11” double-sided page of notes. Show your work on all problems. If you find a problem unclear or underspecified, please ask for clarification of the assumptions. If you make assumptions not listed in the problem, please state them clearly in your solutions. Good luck! Your name: SOLUTION SET SID number: Email address: 1 20 /20 2 20 /20 3 40 /40 4 20 /20 Total 100 /100
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2 Question 1: Being Precise This problem explores some of the issues involved in supporting precise interrupts in a simple 5- stage DLX-like pipeline. (a) Give a simple definition of precise interrupts/exceptions. (3 points) An interrupt/exception is considered precise if there is a single instruction (or interrupt point) for which all instructions preceding that instruction have committed their state and no following instructions, including the interrupting instruction, have modified any state. (b) Why are precise interrupts/exceptions useful? Give 3 examples. (3 points) The following are some of the many possibilities: to provide the restartability needed to implement virtual memory/paging to handle IEEE floating-point exceptions to simulate unimplemented instructions in software to allow fast interrupt handling/context switching to simplify debugging by providing a consistent view of the program’s state to reduce the amount of state needed to be saved by the operating system (c) Draw a simple block diagram of a 5-stage DLX pipeline, including bypass paths to the execu- tion unit (ALU). Do not include the sign-extension hardware or the hardware needed to opti- mize conditional branches (as presented in class). Be sure to label the pipeline stages. (5 points) Instr. Mem P C 4 + M u x IF/ID MEM/WB EX/MEM ID/EX Reg. File A L U M u x M u x Forwarding paths are shown with dotted lines Zero? Data Mem. S. Ext M u x
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3 Question 1 (continued) (d) Consider the following simple instruction sequence: (1) lw r2, 10(r1) ; instruction 1 (2) add r4, r3, r1 ; instruction 2 (3) sub r5, r1, r10 ; instruction 3 Assume that this sequence completes correctly. Using single letters to represent each pipeline stage (F, D, X, M, W), show the time evolution of this sequence (lining up the phases of each instruction): (1 point) TIME lw F D X M W add F D X M W sub F D X M W Notice that I put time on the horizontal axis. This is the traditional way of making these time- evolution pipeline diagrams, as it makes it easy to see what’s happening in a given cycle by taking a vertical slice of the diagram. (e) Now assume the following exceptions occur: instruction 1 gets a data TLB fault; instruction 2 gets an overflow; and instruction 3 causes an instruction TLB fault. Produce a diagram as in part (d), with the faulting stages labeled. (1 point) TIME lw F D X M W add F D X M W sub F D X M W (f) Which exception happens first in time ? (1 point) The ITLB fault for instruction 3 ( sub r5, r1, r10 ) (g)
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