{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Fall99-prerequisite quiz

Computer Architecture: A Quantitative Approach, 4th Edition

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Prerequisite Quiz September 1, 1999 CS252 Computer Architecture and Engineering This prerequisite quiz will be used in determining class admissions. Good Luck! Your Name: SID Number: Discussion Section: 1 2 3 Total
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 1) Assume that we have a 32-bit processor with 32-bit words, and that this processor is byte-addressed (i.e. addresses specify bytes). Now, suppose that this processor has a 32-word, two-way, set- associative cache (LRU replacement) with 2-word cache lines. a) Split the 32-bit address into “tag”, “index”, and “cache-line offset” pieces. We start you off with one of these. tag: index: cache-line offset: bits 2 - 0 b) Assume that the processor makes the following byte accesses. Label each reference address as a Hit (H) or a Miss (M). Also, identify each cache miss as a compulsory, conflict, or capacity miss. Blank working space is available on the next page. Byte Address
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 9

Fall99-prerequisite quiz - University of California...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon bookmark
Ask a homework question - tutors are online