Computer Architecture: A Quantitative Approach, 4th Edition

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Prerequisite Quiz September 1, 1999 CS252 Computer Architecture and Engineering This prerequisite quiz will be used in determining class admissions. Good Luck! Your Name: SID Number: Discussion Section: 1 2 3 Total
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2 1) Assume that we have a 32-bit processor with 32-bit words, and that this processor is byte-addressed (i.e. addresses specify bytes). Now, suppose that this processor has a 32-word, two-way, set- associative cache (LRU replacement) with 2-word cache lines. a) Split the 32-bit address into “tag”, “index”, and “cache-line offset” pieces. We start you off with one of these. tag: index: cache-line offset: bits 2 - 0 b) Assume that the processor makes the following byte accesses. Label each reference address as a Hit (H) or a Miss (M). Also, identify each cache miss as a compulsory, conflict, or capacity miss. Blank working space is available on the next page.
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