Computer Architecture: A Quantitative Approach, 4th Edition

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I October 13, 1999 CS252 Graduate Computer Architecture Your Name: SID Number: Discussion Section: Problem Possible Score 1 20 2 20 3 35 4 25 Total 100
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2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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3 Question #1: Short Answer 1a) Give a simple definition of precise interrupts/exceptions: 1b) Explain how the presence of delayed branches complicates the description of a precise exception point (think about information that the operating system needs to continue execution after an exception)? 1c) The Alpha 21064 (first version of the Alpha processor) supported precise exceptions for virtual memory but not for floating point operations. What sort of argument might be used to justify this complicated combination of behaviors? 1d) Explain the relationship between support for precise exceptions and support for branch prediction. What hardware structure supports both of these mechanisms in a modern out-of- order pipeline?
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5 1e) When is it better to handle events via interrupts rather than polling? How about the reverse? Be specific. 1f) Name 3 different things that people try to predict in modern processors: 1g) Why is branch prediction desirable? 1h) Draw a simple diagram for each of the following branch predictors: GAg, PAg, PAp 1i) Explain the difference between implicit and explicit register renaming as defined in class:
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6 Problem #2: Superpipelining Suppose that we have single-issue, in-order pipeline with one fetch stage, one decode stage, multiple execution stages (which include memory access) and a singe write-back stage. Assume that it has the following execution latencies (i.e. the number of stages that it takes to compute a value): multf (5 cycles), addf (3 cycles), divf (2 cycles), integer ops (1 cycle). Assume full bypassing and two cycles to perform memory accesses, i.e. loads and stores take a total of 3 cycles to execute (with address computation). Finally, branch conditions are computed by the integer execution unit..
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