Computer Architecture: A Quantitative Approach, 4th Edition

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm II December 1, 1999 CS252 Graduate Computer Architecture Your Name: SID Number: Problem Possible Score 12 5 22 5 32 0 43 0 Total 100
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2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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3 Question #1: Prediction 1a) Why does branch prediction work? 1b) What is the aliasing problem for branch predictors? Is aliasing always bad? 1c) How does the branch target buffer (BTB) help modern branch predictors? ( hint: we want to be able to remove all branch delay slots): 1d) Draw the hardware for a gshare branch predictor. Why does this type of predictor generally perform better than an equivalent GAg branch predictor?
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4 1e) For correct performance, out-of-order processors must detect and resolve RAW, WAR, and WAW hazards between loads and stores to memory. Describe the hardware support for detecting these hazards and provide a short, pseudo-code description of the questions that must be asked before a load or store is released to the memory system. Assume no dependence speculation for the moment (conservative removal of hazards). 1f) “Naive dependence speculation” assumes that loads and stores are not dependent on each other, if their addresses are unknown. How does this change your algorithm above? On average, is this a better idea than being exact (as in 1e)? Why or why not?
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5 1g) What is memory dependence prediction and why does it help to improve performance in an modern processor with-out-of-order execution? ( hint: compare with naive dependence speculation)? 1h) What hardware might be used to detect and predict repeating patterns of four or less data values (e.g. something like: 4, 5, 6, 2, 4, 5, 6, 2, etc. ..)? Assume that these are 32-bit values. 1i) How might data prediction be used in a modern processor? Under what circumstances might this improve performance (try to be specific, i.e. don’t just say “when it is correct”)?
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7 Problem #2: Error Correction and RAID The error correction coding process can be viewed as a transformation from one space of bits (the unencoded data) to another (the coded data). 2a) In the (n,k) notation for an error correction code, k is the unencoded data width in bits and n is the encoded width. Which is larger, n or k ? Why must it be this way?
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This homework help was uploaded on 01/29/2008 for the course CS 252 taught by Professor Kubiatowicz during the Fall '07 term at University of California, Berkeley.

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f99-quiz2 - University of California, Berkeley College of...

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