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Unformatted text preview: Design Compiler® User Guide Version X-2005.09, September 2005 Comments? Send comments on the documentation by going to , then clicking “Enter a Call to the Support Center.” Copyright Notice and Proprietary Information Copyright © 2005 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: “This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.” Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Registered Trademarks (®) Synopsys, AMPS, Arcadia, C Level Design, C2HDL, C2V, C2VHDL, Cadabra, Calaveras Algorithm, CATS, CRITIC, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM, HSPICE, Hypermodel, iN-Phase, in-Sync, Leda, MAST, Meta, Meta-Software, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill, PrimeTime, RailMill, RapidScript, Saber, SiVL, SNUG, SolvNet, Superlog, System Compiler, Testify, TetraMAX, TimeMill, TMA, VCS, Vera, and Virtual Stepper are registered trademarks of Synopsys, Inc. Trademarks (™) Active Parasitics, AFGen, Apollo, Apollo II, Apollo-DPII, Apollo-GA, ApolloGAII, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanTestchip, AvanWaves, BCView, Behavioral Compiler, BOA, BRT, Cedar, ChipPlanner, Circuit Analysis, Columbia, Columbia-CE, Comet 3D, Cosmos, CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, Cyclelink, Davinci, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Vision, DesignerHDL, DesignTime, DFM-Workbench, Direct RTL, Direct Silicon Access, Discovery, DW8051, DWPCI, Dynamic Model Switcher, Dynamic-Macromodeling, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ, Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, Galaxy, Gatran, HANEX, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II, Hierarchical plus Optimization Technology, High Performance Option, HotPlace, HSIM , HSPICE-Link, i-Virtual Stepper, iN-Tandem, Integrator, Interactive Waveform Viewer, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme, Liberty, Libra-Passport, Libra-Visa, Library Compiler, Magellan, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture, Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, Nova Product Family, Nova-ExploreRTL, Nova-Trans, Nova-VeriLint, Nova-VHDLlint, Optimum Silicon, Orion_ec, Parasitic View, Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate, ProFPGA, ProGen, Prospector, Protocol Compiler, PSMGen, Raphael, Raphael-NES, RoadRunner, RTL Analyzer, Saturn, ScanBand, Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint, Silicon Early Access, SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC, Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-SimXT, Star-Time, Star-XP, SWIFT, Taurus, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True-Hspice, TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Inc. Service Marks (SM) MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. All other product or company names may be trademarks of their respective owners. Printed in the U.S.A. Document Order Number: 36042-000 ZA Design Compiler User Guide, version X-2005.09 ii Contents What’s New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxi 1. Introduction to Design Compiler Design Compiler and the Design Flow . . . . . . . . . . . . . . . . . . . . . . 1-2 Design Compiler Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 DC Expert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 DC Ultra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 HDL Compiler Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 DesignWare Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 DFT Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Module Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Power Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Design Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Design Compiler FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 iii 2. Design Compiler Basics The High-Level Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Running Design Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Design Compiler Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Design Compiler Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Setup Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Starting Design Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Exiting Design Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Getting Command Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Using Command Log Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Using the Filename Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Using Script Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Working with Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Listing the Licenses in Use. . . . . . . . . . . . . . . . . . . . . . . . . . Getting Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Releasing Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2-17 2-17 2-17 Following the Basic Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . 2-18 A Design Compiler Session Example . . . . . . . . . . . . . . . . . . . . . . . 2-25 3. Preparing Design Files for Synthesis iv Managing the Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Controlling the Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Organizing the Design Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Partitioning for Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Partitioning for Design Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Keeping Related Combinational Logic Together . . . . . . . . . . . . 3-5 Registering Block Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Partitioning by Design Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Partitioning by Compile Technique. . . . . . . . . . . . . . . . . . . . . . . 3-9 Keeping Sharable Resources Together . . . . . . . . . . . . . . . . . . . 3-10 Keeping User-Defined Resources With the Logic They Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Isolating Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 HDL Coding for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Writing Technology-Independent HDL . . . . . . . . . . . . . . . . . . . . Inferring Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Synthetic Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . Designing State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-14 3-18 3-21 Using HDL Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General HDL Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Verilog Macro Definitions . . . . . . . . . . . . . . . . . . . . . . Using VHDL Port Definitions . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3-22 3-27 3-28 Writing Effective Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for Expressions. . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3-28 3-30 3-31 3-33 4. Working With Libraries Selecting a Semiconductor Vendor . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Understanding the Library Requirements . . . . . . . . . . . . . . . . . . . . 4-3 Technology Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 v Symbol Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 DesignWare Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Specifying Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Specifying Technology Libraries . . . . . . . . . . . . . . . . . . . . . . . . Target Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-7 4-7 Specifying DesignWare Libraries. . . . . . . . . . . . . . . . . . . . . . . . 4-10 Specifying a Library Search Path. . . . . . . . . . . . . . . . . . . . . . . . 4-10 Loading Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Listing Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Reporting Library Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Specifying Library Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Directing Library Cell Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Excluding Cells From the Target Library . . . . . . . . . . . . . . . . . . 4-13 Specifying Cell Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Removing Libraries From Memory . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Saving Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 5. Working With Designs in Memory vi Design Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 About Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flat Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hierarchical Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-3 5-3 Design Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Relationship Between Designs, Instances, and References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Reference Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5-7 Design Database Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Reading Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Commands for Reading Design Files . . . . . . . . . . . . . . . . . . . . 5-10 Using the analyze and elaborate Commands . . . . . . . . . . . 5-10 Using the read_file Command . . . . . . . . . . . . . . . . . . . . . . . 5-12 Using the read_milkyway command . . . . . . . . . . . . . . . . . . . . . 5-14 Reading HDL Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Reading .ddc Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Reading .db Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Listing Designs in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Setting the Current Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Using the current_design Command . . . . . . . . . . . . . . . . . . . . . 5-18 Linking Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Locating Designs by Using a Search Path. . . . . . . . . . . . . . . . . 5-21 Changing Design References . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Listing Design Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Specifying Design Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Using a Relative Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Using an Absolute Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 Creating Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 Copying Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 vii Renaming Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 Changing the Design Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 Adding Levels of Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 Grouping Cells Into Subdesigns. . . . . . . . . . . . . . . . . . . . . . 5-32 Grouping Related Components Into Subdesigns . . . . . . . . . 5-34 Removing Levels of Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . Ungrouping Hierarchies Before Optimization . . . . . . . . . . . . Ungrouping Hierarchies During Optimization . . . . . . . . . . . . Preserving Hierarchical Pin Timing Constraints During Ungrouping. . . . . . . . . . . . . . 5-35 5-36 5-39 5-44 Merging Cells From Different Subdesigns . . . . . . . . . . . . . . . . . 5-46 Editing Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 Translating Designs From One Technology to Another . . . . . . . . . . 5-50 Procedure to Translate Designs. . . . . . . . . . . . . . . . . . . . . . . . . 5-50 Restrictions on Translating Between Technologies . . . . . . . . . . 5-51 Removing Designs From Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 Saving Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 Commands to Save Design Files. . . . . . . . . . . . . . . . . . . . . . . . 5-54 Using the write Command . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 Using the write_milkyway Command . . . . . . . . . . . . . . . . . . 5-55 Saving Designs in .ddc Format . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 Saving Designs in the .db Format . . . . . . . . . . . . . . . . . . . . . . . 5-56 Converting From .db Format to .ddc Format . . . . . . . . . . . . . . . 5-57 Ensuring Name Consistency Between the Design Database and the Netlist . . . . . . . . . . . . . . . . . . . . . 5-57 Naming Rules Section of the .synopsys_dc.setup File . . . . 5-57 viii Using the define_name_rules -map Command . . . . . . . . . . 5-58 Resolving Naming Problems in the Flow . . . . . . . . . . . . . . . 5-59 Working With Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 Setting Attribute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 Using an Attribute-Specific Command . . . . . . . . . . . . . . . . . 5-64 Using the set_attribute Command . . . . . . . . . . . . . . . . . . . . 5-64 Viewing Attribute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 Saving Attribute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66 Defining Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66 Removing Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66 The Object Search Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 6. Defining the Design Environment Defining the Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Determining Available Operating Condition Options . . . . . . . . . 6-4 Specifying Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Defining Wire Load Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Hierarchical Wire Load Models . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Determining Available Wire Load Models . . . . . . . . . . . . . . . . . 6-9 Specifying Wire Load Models and Modes . . . . . . . . . . . . . . . . . 6-11 Modeling the System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Defining Drive Characteristics for Input Ports . . . . . . . . . . . . . . 6-13 The set_driving_cell Command . . . . . . . . . . . . . . . . . . . . . . 6-14 The set_drive and set_input_transition Commands . . . . . . . 6-15 Defining Loads on Input and Output Ports. . . . . . . . . . . . . . . . . 6-17 Defining Fanout Loads on Output Ports. . . . . . . . . . . . . . . . . . . 6-18 ix 7. Defining Design Constraints Setting Design Rule Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Setting Transition Time Constraints . . . . . . . . . . . . . . . . . . . . . . 7-4 Setting Fanout Load Constraints . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Setting Capacitance Constraints . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Setting Optimization Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Setting Timing Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining a Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying I/O Timing Requirements . . . . . . . . . . . . . . . . . . Specifying Combinational Path Delay Requirements . . . . . . Specifying Timing Exceptions . . . . . . . . . . . . . . . . . . . . . . . 7-10 7-11 7-14 7-16 7-17 Setting Area Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 Verifying the Precompiled Design . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 8. Optimizing the Design The Optimization Process . . . . . . . . . . . . . . . . . . . ....
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