l13_15a_2rev

# l13_15a_2rev - ECE 15A Fundamentals of Logic Design Lecture...

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1 ECE 15A Fundamentals of Logic Design Lecture 13 Malgorzata Marek-Sadowska Electrical and Computer Engineering Department UCSB 2 Test #2 study plan ± Multi-level circuit realizations, conversion between forms ± Timing diagrams, hazards ± Quine-McCluskey and Petrick’s methods; prime implicants and essential prime implicants ± Finding tests for stuck-at faults ± Multiplexers ² As circuit elements ² Expansions ± 3-state buffers

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2 3 Today: Programmable Logic ± Programmable digital integrated circuit ² Off-the-shelf parts ² Customized by configuring on-chip logic blocks and interconnections ± Advantages (compared to an ASIC): ² Low development costs ² Short development cycle ² Device can (usually) be reprogrammed ± Types of programmable logic: ² Complex PLDs (CPLD), PALs ² Field programmable Gate Arrays (FPGA) 4 Programmable Logic Devices (PLDs) ± The big idea: Program pre-fabricated circuit elements to perform the desired logical operation ± Regular structure logic devices that can be programmed to implement any combinational logic circuit. ± Programmed Æ refers to a hardware process used to specify the logic that a PLD implements
3 5 Gate Symbols . . . Conventional AND gate symbol ... Array Logic AND gate symbol a b c F F = abc ab c F = 0 F = ac 6 PLD - Sum of Products ABC AND plane Programmable AND array followed by fixed fan-in OR gates Programmable switch or fuse C B A B A f + = 2 C B A C B A f + = 1

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4 7 PLD - Macrocell Can implement combinational or sequential logic A B C Flip-flop Select Enable DQ Clock AND plane MUX 1 f 8 CPLD Structure Integration of several PLD blocks with a programmable interconnect on a single chip PLD Block PLD Block PLD Block PLD Block I/O Block PLD Block PLD Block PLD Block PLD Block Interconnection Matrix
5 9 Programmable Array Logic (PAL) ± OR plane (array) is fixed, AND plane can be programmed ± # of product terms available per function (OR outputs) is limited 10 PAL Example inputs 1 st output section 2 nd output section 3 rd output

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## This note was uploaded on 05/29/2009 for the course ECE 15A taught by Professor M during the Winter '08 term at UCSB.

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l13_15a_2rev - ECE 15A Fundamentals of Logic Design Lecture...

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