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ECE 15A
Fundamentals of Logic Design
Lecture 9
Malgorzata Marek-Sadowska
Electrical and Computer Engineering Department
UCSB
2
Multi-Level Logic: Advantages
Reduced sum of products form:
x
= A D F
+
A E F
+
B D F
+
B E F
+
C D F
+
C E F
+
G
6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)
25 wires (19 literals plus 6 internal wires)
Factored form:
x
= (A + B + C) (D + E) F
+
G
1 x 3-input OR gate, 2 x 2-input OR gates,
1 x 3-input AND gate
10 wires (7 literals plus 3 internal wires)
1
2
3
4
5
6
7
A
A
B
B
C
C
D
D
D
E
E
E
F
F
F
F
F
F
G
x
1
2
3
4
A
B
C
D
E
F
G
x

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Multi-Level Logic:
CAD Tools for Simplification
Multi-Level Optimization:
1.
Factor out common sublogic (reduce fan-in, increase gate
levels),
subject to timing constraints
2.
Map factored form onto library of gates
3.
Minimize number of literals (correlates with number of wires)
4
Multi-Level Logic:
CAD Tools for Simplification
Factoring:
expression in two level form
re-expressed in multi-level form
F = A C
+
A D
+
B C
+
B D
+
E
can be rewritten as:
F = (A + B) (C + D) + E
(9 literals & 5 gates)
(7 literals & 4 gates)
Before Factoring
After Factoring
A
A
A
B
B
B
C
C
C
D
D
D
E
E
F
F