CS152-S04-HW4-Solutions

Computer Organization and Design: The Hardware/Software Interface

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HW4 Solutions – Spring 2004 – Kubi 6.2, 6.3, 6.4, 6.9, 6.15, 6.18, 6.19, 6.21, 6.23, 6.26, 6.27, 6.28, 6.29, 6.31 6.2 6.3 6.4 6.9 6.15 Dependencies: One from MEM/WB of inst N to IDEX of inst N+1 Resolution: Insert stall between inst N and N+1 Total # cycles: 8
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6.18 6.19 6.21 If there were no address calculations for memory ops, then there would be no single instruction that uses both MEM and ALU stages. Therefore, we could combine those two stages into a single one with no significant increase in cycle time (turn it into a four stage
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Unformatted text preview: pipeline) – other than the addition of some muxes. Forwarding would be simpler, as forwarding cases increases with the square of the number of stages. 6.23 6.26 6.27 6.28 6.29 6.31 Loop: Sltiu $at $s1 12 Bne $at $0 Cleanup Lw $t0 0($s1) Lw $t1 -4($s1) Lw $t2 -8($s1) Addu $t0 $t0 $s2 Addu $t1 $t1 $s2 Addu $t2 $t2 $s2 Sw $t0 0($s1) Sw $t1 -4($s1) Sw $t2 -8($s1) J Loop Addiu $s1 $s2 -12 # delay slot Cleanup: Beq $s1 $0 Done Lw $t0 0 ($s1) Addu $t0 $t0 $s2 Sw $t0 0($s1) J Cleanup Addiu $s1 $s2 -4 # delay slot Done:...
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This homework help was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at Berkeley.

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CS152-S04-HW4-Solutions - pipeline) – other than the...

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