Computer Organization and Design: The Hardware/Software Interface

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University of California, Berkeley - College of Engineering Electrical Engineering and Computer Science, Computer Science Division Spring 2004 J. Kubiatowicz CS152 - Computer Architecture and Engineering Homework #5 Solutions 7.7 7.9 7.11 7.12 7.15 AMAT = Hit time + Miss Time*Miss penalty AMAT = 2ns + (20*2ns) * 0.05 = 4ns 7.16 AMAT = (1.2*2ns) + (20*2ns*0.03) = 2.4ns + 1.2ns = 3.6ns. Yes, this is a good choice.
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7.18 7.23 Two principles apply to this cache behavior problem. First, a two-way set-associative cache of the same size as a direct-mapped cache has half the number of sets. Second, LRU replacement can behave pessimally (as poorly as possible) for access patterns that cycle through a sequence of addresses that reference more blocks than will fit in a set managed by LRU replacement. One example is the following memory address references: Assuming that cache size is 16 , the address is word address and each cache block is one word. 1, 2, 17, 33, 1,2
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This homework help was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at Berkeley.

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CS152-S04-HW5-Solutions - University of California Berkeley...

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