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Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2004 John Kubiatowicz Homework Quiz (HW #5) April 26, 2004 CS152 Computer Architecture and Engineering This quiz combines two of the problems from homework #5. Good Luck! Your Name: SID Number: Discussion Section: Total:
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3 Cache organization Your company has an application that must be run as fast as possible. The hardware division of your company has come up with three separate first-level cache configurations: Machine I: Direct-mapped with one-word blocks Machine II: Direct-mapped with four-word blocks Machine III: Two-way set associative with four-word blocks For each of these machines, the cache fill penalty is 6 cycles + 1 cycle for each word. You did some experiments and measured the following instruction mix for the application:
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Unformatted text preview: Branch: 20%, Load: 13%, Store: 12%, Float Insts: 20%, Integer: 35% Further, through a hardware cache monitor, you measured the following miss rates: • Machine I: Instruction miss rate: 4%; Data miss rate: 20% • Machine II: Instruction miss rate: 2%; Data miss rate: 16% • Machine III: Instruction miss rate: 1.5%; Data miss rate: 14% Finally, the total CPI measured with Machine I is 3.0. 1. Which machine spends the most time waiting for memory? Justify your answer (no guesses!): 2. What is the CPI for Machine III? 3. Suppose that these machines run at 100Mhz (10ns cycle time). What is the average memory access time (AMAT) for each of these machines (in nanoseconds) assuming that machines I and II have a 1 cycle hit time and machine III has a 2 cycle hit time?...
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homequiz_5 - Branch 20 Load 13 Store 12 Float Insts 20...

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