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Computer Organization and Design: The Hardware/Software Interface

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Lab 3: Single Cycle Processor CS152 Computer Architecture and Engineering Lab #3: Single Cycle Processor Spring 2004, Prof. John Kubiatowicz Lab reports for Lab 3 due Thursday 3/11 at 11:59pm via the submit program. You will demonstrate your lab to your TA on Thursday, 3/11 in section. During this demo, the TA will provide you with secret test code. If you are able to pass these tests on your first try, you will receive bonus points. If you fail the first time, then your TA will give you the source code to the tests and you will have until the end of the day to complete the tests for full credit. If you are not done by the end of the day then you will lose points for each additional day that you are late. This is the first lab to be done in groups. Like the previous labs, this lab is rather long, so get started early!!! Homework Policy: Homework assignments are due in class. No late homeworks will be accepted. There will be a short quiz in lecture the day the assignment is due; the quiz will be based on the homework. Study groups are encouraged, but what you turn in must be your own work. Lab Policy : Labs (including final reports) must be submitted by 11:59pm on the day that your lab is checked off. To Submit your lab report, run m:\bin\submit-spring2004.exe or at command prompt, type " submit-spring2004.exe " then follow the instructions. Make sure you input the correct section number, and directory to submit. Remember that you can only submit once, so make sure to submit only when you're ready. Otherwise your lab/project grade will NOT be correctly recorded. The required format for lab reports is shown on the handouts page. Homework 3 Please do the following problems from P&H: 4.44, 4.46, 5.2, 5.11, 5.17, 5.18, 5.20, 5.21, 5.22, 5.24, 5.27, 5.28, 5.29 Lab 3 file:///C|/Documents%20and%20Settings/Linda%20Grauer. ..es/Berkeley-Harvest/CS%20152/Sp04/homeworklab_3.html (1 of 8) [1/29/2008 3:03:05 PM]
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Lab 3: Single Cycle Processor In this assignment you will build a single-cycle datapath like the one discussed in class and in chapter 5 of the book, and verify that it executes a subset of the MIPS instruction set. This lab has two goals: (1) getting you more familiar with Verilog and the mixing of Verilog and schematics. (2) constructing a complete working single-cycle datapath. This lab assignment is to be completed with your project partners. Each group should elect a spokesperson for this lab, which should be stated in the design document. The responsibility of the spokesperson is to communicate questions to the TA and reply to questions from the TA. For each lab, you will need to select a different spokesperson. Problem 0.5: Design Document Please review this assignment with your partners. A formal design document (which we will go over in section) and a division of labor is due via e-mail to your TA Wednesday 2/25 by 9pm. This will allow the TAs time to go over your design document with you during section on Thursday 2/26. You are encouraged to finish this first version of your design document and turn it in as early as possible, so that
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homeworklab_3 - Lab 3 Single Cycle Processor CS152 Computer...

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