Computer Organization and Design: The Hardware/Software Interface

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CS152 Lab #5: The Memory Subsystem CS152 Computer Architecture and Engineering Homework/Lab #5: The Memory Subsystem Spring 2004, Prof. John Kubiatowicz A formal design document and a division of labor is due via e-mail to your TA Wednesday 4/7 by 9pm . This will allow the TAs time to go over your design document with you during section on Thursday 4/8 . You are encouraged to finish your design document and turn it in as early as possible, so that the TA can review it earlier, which will allow you to begin working on this lab earlier. . Lab reports for Lab 5 due Thursday 4/22 at 11:59pm via the submit program. You will demonstrate your lab to your TA on Thursday 4/15 and Thursday 4/22 in section. During this demos, the TA will provide you with secret test code. If you are able to pass these tests on your first try, you will receive bonus points. If you fail the first time, then your TA will give you the source code to the tests and you will have until the end of the day to complete the tests for full credit. If you are not done by the end of the day then you will lose points for each additional day that you are late. We like to call this lab the "Widowmaker" (just ask Jack and John what happened last Spring), so you should get started now!!!! Homework Policy: Homework assignments are due in class. No late homeworks will be accepted. There will be a short quiz in lecture the day the assignment is due; the quiz will be based on the homework. Study groups are encouraged, but what you turn in must be your own work. Lab Policy : Labs (including final reports) must be submitted by 11:59pm on the day that your lab is checked off. To Submit your lab report, run m:\bin\submit-spring2004.exe or at command prompt, type " submit- spring2004.exe " then follow the instructions. Make sure you input the correct section number, and directory to submit. Remember that you can only submit once, so make sure to submit only when you're ready. Otherwise your lab/ project grade will NOT be correctly recorded. The required format for lab reports is shown on the handouts page. Homework 5: Please do the following problems from P&H: 7.7, 7.9, 7.11, 7.12, 7.15, 7.16, 7.18, 7.23, 7.24, 7.27, 7.32, 7.36, 8.8, 8.13, 8.19, 8.22, 8.29 Homework assignments should continue to be done individually. This homework is due Monday 4/26. Lab 5: In this lab, you will be designing a memory system for your pipelined processor. The previous memory module was far file:///C|/Documents%20and%20Settings/Linda%20Grauer/My%20Documents/Dolores/Berkeley-Harvest/CS%20152/Sp04/homeworklab_5.html (1 of 19) [1/29/2008 3:03:44 PM]
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CS152 Lab #5: The Memory Subsystem from practical, and you will never have separate, dedicated DRAM banks for instructions and data. Using a realistic main memory system will cause two problems in your pipelined processor: (1) your cycle time will dramatically increase as a result of the main memory write and read latency and (2) you must handle conflicts when both data and instruction
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This lab report was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at University of California, Berkeley.

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homeworklab_5 - CS152 Lab #5: The Memory Subsystem CS152...

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