I/O and Queueing theory

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 23 I/O and Storage Systems April 26, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 4/26/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec23.2 Recap: A Three-Bus System (+ backside cache) ° A small number of backplane buses tap into the processor-memory bus Processor-memory bus is only used for processor-memory traffic I/O buses are connected to the backplane bus ° Advantage: loading on the processor bus is greatly reduced Processor Memory Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus Backside Cache bus I/O Bus L2 Cache 4/26/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec23.3 Recap: Main components of Intel Chipset: Pentium II/III ° Northbridge: Handles memory Graphics ° Southbridge: I/O PCI bus Disk controllers USB controlers Audio Serial I/O Interrupt controller Timers 4/26/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec23.4 ° One of the most important issues in bus design: How is the bus reserved by a device that wishes to use it? ° Chaos is avoided by a master-slave arrangement: Only the bus master can control access to the bus: It initiates and controls all bus requests A slave responds to read and write requests ° The simplest system: Processor is the only bus master All bus requests must be controlled by the processor Major drawback: the processor is involved in every transaction Bus Master Bus Slave Control: Master initiates requests Data can go either way Arbitration: Obtaining Access to the Bus
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4/26/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec23.5 The Daisy Chain Bus Arbitrations Scheme ° Advantage: simple ° Disadvantages: Cannot assure fairness: A low-priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed Bus Arbiter Device 1 Highest Priority Device N Lowest Priority Device 2 Grant Grant Grant Release Request wired-OR 4/26/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec23.6 ° Used in essentially all processor-memory busses and in high- speed I/O busses Bus Arbiter Device 1 Device N Device 2 Grant Req Centralized Parallel Arbitration 4/26/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec23.7 ° Separate versus multiplexed address and data lines: Address and data can be transmitted in one bus cycle if separate address and data lines are available Cost: (a) more bus lines, (b) increased complexity ° Data bus width: By increasing the width of the data bus, transfers of multiple words require fewer bus cycles Example: SPARCstation 20’s memory bus is 128 bit wide Cost: more bus lines ° Block transfers: Allow the bus to transfer multiple words in back-to-back bus cycles Only one address needs to be sent at the beginning The bus is not released until the last word is transferred Cost: (a) increased complexity (b) decreased response time for request Increasing the Bus Bandwidth 4/26/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec23.8 ° Overlapped arbitration
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I/O and Queueing theory - Recap A Three-Bus System backside...

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