Review of MIPS ISA, Performance

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Design Concepts January 26, 2004 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 1/26/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec2.2 Review: Organization Control Datapath Memory Processor Input Output All computers consist of five components • Processor: (1) datapath and (2) control (3) Memory • I/O: (4) Input devices and (5) Output devices Datapath and Control typically on on chip 1/26/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec2.3 The Instruction Set: a Critical Interface instruction set software hardware 1/26/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec2.4 ISA Choices
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1/26/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec2.5 Data Types Bit : 0, 1 Bit String : sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Character : ASCII 7 bit code UNICODE 16 bit code Decimal : digits 0-9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Integers : 2's Complement Floating Point : Single Precision Double Precision Extended Precision M x R E How many +/- #'s? Where is decimal pt? How are +/- exponents represented? exponent base mantissa 1/26/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec2.6 Instruction Set Architecture: What Must be Specified? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Instruction Format or Encoding • how is it decoded? Location of operands and result • where other than memory? • how many explicit operands? • how are memory operands located? • which can or cannot be in memory? Data type and Size Operations • what are supported Successor instruction • jumps, conditions, branches fetch-decode-execute is implicit! 1/26/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec2.7 Top 10 80x86 Instructions Rank instruction Integer Average Percent total executed 1 load 22% 2 conditional branch 20% 3 compare 16% 4 store 12% 5 add 8% 6 and 6% 7 sub 5% 8 move register-register 4% 9 call 1% 10 return 1% Total 96% Simple instructions dominate instruction frequency 1/26/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec2.8 Operation Summary Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, return;
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1/26/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec2.9 Methods of Testing Condition Condition Codes Processor status bits are set as a side-effect of arithmetic instructions (possibly on Moves) or explicitly by compare or test instructions.
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This note was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at University of California, Berkeley.

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Review of MIPS ISA, Performance - Review: Organization...

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