Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 22 Virtual Memory (continued) Buses April 21, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 4/21/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec22.2 ° Virtual memory => treat memory as a cache for the disk ° Terminology: blocks in this cache are called “Pages” Typical size of a page: 1K — 8K ° Page table maps virtual page numbers to physical frames “PTE” = Page Table Entry Physical Address Space Virtual Address Space Recap: What is virtual memory? Virtual Address Page Table index into page table Page Table Base Reg V Access Rights PA V page no. offset 10 table located in physical memory P page no. offset 10 Physical Address 4/21/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec22.3 Recap: Implementing Large Page Tables Two-level Page Tables 32-bit address: P1 index P2 index page offest 4 bytes 4 bytes 4KB 10 10 12 1K PTEs ° 2 GB virtual address space ° 4 MB of PTE2 – paged, holes ° 4 KB of PTE1 What about a 48-64 bit address space? 4/21/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec22.4 Recap: Making address translation practical: TLB ° Virtual memory => memory acts like a cache for the disk ° Page table maps virtual page numbers to physical frames ° Translation Look-aside Buffer (TLB) is a cache translations Physical Memory Space Virtual Address Space TLB Page Table 2 0 1 3 virtual address page off 2 frame page 2 5 0 physical address page off
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4/21/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec22.5 TLB organization: include protection ° TLB usually organized as fully-associative cache Lookup is by Virtual Address Returns Physical Address + other info ° Dirty => Page modified (Y/N)? Ref => Page touched (Y/N)? Valid => TLB entry valid (Y/N)? Access => Read? Write? ASID => Which User? Virtual Address Physical Address Dirty Ref Valid Access ASID 0xFA00 0x0003 Y N Y R/W 34 0x0040 0x0010 N Y Y R 0 0x0041 0x0011 N Y Y R 0 4/21/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec22.6 Example: R3000 pipeline includes TLB stages Inst Fetch Dcd/ Reg ALU / E.A Memory Write Reg TLB I-Cache RF Operation WB E.A. TLB D-Cache MIPS R3000 Pipeline ASID V. Page Number Offset 12 20 6 0xx User segment (caching based on PT/TLB entry) 100 Kernel physical space, cached 101 Kernel physical space, uncached 11x Kernel virtual space Allows context switching among 64 user processes without TLB flush Virtual Address Space TLB 64 entry, on-chip, fully associative, software TLB fault handler 4/21/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec22.7 What is the replacement policy for TLBs? ° On a TLB miss, we check the page table for an entry. Two architectural possibilities: Hardware “table-walk” (Sparc, among others) - Structure of page table must be known to hardware Software “table-walk” (MIPS was one of the first) - Lots of flexibility - Can be expensive with modern operating systems.
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This note was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at University of California, Berkeley.

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Buses and I/O - Recap: What is virtual memory? CS152...

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