Logic Design, Technology & Delay Modeling

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 3 Logic Design, Technology, and Delay January 28, 2004 John Kubiatowicz ( ) lecture slides: 1/28/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec3.2 Review:MIPS R3000 Instruction Set Architecture ° Register Set 32 general 32-bit registers Register zero ($R0) always zero Hi/Lo for multiplication/division ° Instruction Categories Load/Store Computational - Integer/Floating point Jump and Branch Memory Management Special ° 3 Instruction Formats: all 32 bits wide R0 - R31 PC HI LO OP OP rs rt rd sa funct rs rt immediate Registers jump target OP 1/28/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec3.3 The Design Process "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman does not distinguish between the conceptualization and the artifact -- Separation comes about because of complexity -- The concept is captured in one or more representation languages VERILOG, Schematics, etc. -- This process IS design Design Begins With Requirements -- Functional Capabilities : what it will do -- Performance Characteristics : Speed, Power, Area, Cost, . . . 1/28/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec3.4 Design Process (cont.) Design Finishes As Assembly CPU -- Design understood in terms of components and how they have been assembled -- Top Down decomposition of complex functions (behaviors) into more primitive functions -- bottom-up composition of primitive building blocks into more complex assemblies Datapath Control ALU Regs Shifter Nand Gate Design is a "creative process," not a simple method
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1/28/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec3.5 Design Refinement Informal System Requirement Initial Specification Intermediate Specification Intermediate Specification of Implementation Physical Implementation refinement increasing level of detail 1/28/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec3.6 Logic Components 1/28/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec3.7 ° Wires: Carry signals from one point to another Single bit (no size label) or multi-bit bus (size label) ° Combinational Logic: Like function evaluation Data goes in, Results come out after some propagation delay ° Flip-Flops: Storage Elements After a clock edge, input copied to output Otherwise, the flip-flop holds its value Also: a “Latch” is a storage element that is level triggered D Q D[8] Q[8] 8 Combinational Logic 11 8 Elements of the design zoo 1/28/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec3.8 Basic Combinational Elements+DeMorgan Equivalence Wire Inverter In Out 0 1 0 1 In Out 1 0 0 1 Out In Out = In Out = In NAND Gate NOR Gate A B Out 1 1 1 0 0 0 1 1 0 1 1 0 A B Out 0 0 1 0 1 0 1 0 0 1 1 0 Out A B A B Out DeMorgan’s Theorem Out = A + B = A • B Out = A • B = A + B A B Out A B Out 1 1 1 1 0 1 0 1 1 0 0 0 0 0 0 1 1 0 1 1 A B Out A B A B Out 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 A B
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1/28/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec3.9 General C/L Cell Delay Model ° Combinational Cell (symbol) is fully specified by: functional (input -> output) behavior - truth-table, logic equation, VHDL Input load factor of each input
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