High-Level design and FPGA

# Computer Organization and Design: The Hardware/Software Interface

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• davidvictor
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CS152 Computer Architecture and Engineering Lecture 5 High-Level Design FPGAs/Vertex-E Chipset February 9, 2004 John Kubiatowicz ( ) lecture slides: 2/9/034 ©UCB Spring 2004 CS152 / Kubiatowicz Lec5.2 Review: Elements of the Design Process ° Divide and Conquer (e.g., ALU) Formulate a solution in terms of simpler components. Design each of the components (subproblems) ° Generate and Test (e.g., ALU) Given a collection of building blocks, look for ways of putting them together that meets requirement ° Successive Refinement (e.g., multiplier, divider) Solve "most" of the problem (i.e., ignore some constraints or special cases), examine and correct shortcomings. ° Formulate High-Level Alternatives (e.g., shifter) Articulate many strategies to "keep in mind" while pursuing any one approach. ° Work on the Things you Know How to Do The unknown will become “obvious” as you make progress. 2/9/034 ©UCB Spring 2004 CS152 / Kubiatowicz Lec5.3 Review: ALU Design ° Bit-slice plus extra on the two ends ° Overflow means number too large for the representation ° Carry-look ahead and other adder tricks ALU0 a0 b0 cin co s0 ALU31 a31 b31 cin co s31 B 32 signed-arith and cin xor co 32 A M 4 C/L to produce select, comp, c-in Ovflw 32 S 2/9/034 ©UCB Spring 2004 CS152 / Kubiatowicz Lec5.4 Review: Carry Look Ahead (Design trick: peek) A0 B0 A1 B1 A2 B2 A3 B3 S S S S G P G P G P G P C1 = G0 + C0 P0 C2 = G1 + G0 P1 + C0 P0 P1 C3 = G2 + G1 P2 + G0 P1 P2 + C0 P0 P1 P2 G C4 = . . . P A B C-out 0 0 0 “kill” 0 1 C-in “propagate” 1 0 C-in “propagate” 1 1 1 “generate” G = A and B P = A xor B C0 = Cin

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