Verilog (finished), Multiplication

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 6 Verilog (finish) Multiply, Divide, Shift February 11, 2004 John Kubiatowicz ( ) lecture slides: 2/11/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec6.2 Review from last time ° Design Process Design Entry: Schematics, HDL, Compilers High Level Analysis: Simulation, Testing, Assertions Technology Mapping: Turn design into physical implementation Low Level Analysis: Check out Timing, Setup/Hold, etc ° Verilog – Three programming styles Structural: Like a Netlist - Instantiation of modules + wires between them Dataflow: Higher Level - Expressions instead of gates Behavioral: Hardware programming - Full flow-control mechanisms - Registers, variables - File I/O, consol display, etc 2/11/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec6.3 Verilog subtlety: Blocking Assignments ° Blocking Assignments: • Assignments happen more like programming language (sequential code) • Both Right and left sides evaluated completely • Wait until assignment before going on - Can cause unexpected results when connecting output to logic in other always blocks. - Also a bit strange with delays on left hand side (LHS) ° Example: reg E, C; always @(posedge clk) begin E = ~A; C = ~E; end A E C 2/11/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec6.4 Verilog subtlety: Non-Blocking Assignments ° Non-blocking Assignments: • All right-hand sides evaluated immediately • Then assignments occur • If no delays, often want output ports to be assigned with non-blocking assignments ° Example: reg E, C; always @(posedge clk) begin E <= ~A; C <= ~E; end A C E
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2/11/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec6.5 Sequential Logic (Revisited: better scheduling) Must be careful mixing zero-time blocking assignments and edge-triggering: Probably won’t do what you expect when connecting it to other things! module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ ( posedge CLK) Q = #5 D; endmodule // FF Good: Outputs 5 units “after edge” module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ ( posedge CLK) Q <= D; endmodule // FF Good: Doesn’t output until “after edge” module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ ( posedge CLK) #5 Q = D; endmodule // FF Probably Not what you Expect: Hold time of 5 units glitches < 5 units ignored 2/11/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec6.6 A final word on Verilog ° Verilog does not turn hardware design into writing programs! Since Verilog looks similar to programming languages, some think that they can design hardware by writing programs. - NOT SO . Verilog is a hardware description language. - The best way to use it is to first figure out the circuit you want, then figure out how to describe it in Verilog. The behavioral construct hides a lot of the circuit details but you as the designer must still manage: - the structure - data-communication - Parallelism - timing of your design.
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