Computer Organization and Design: The Hardware/Software Interface

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2/18/03 ©UCB Spring 2004 CS152 / Kubiatowicz Lec7.1 CS152 Computer Architecture and Engineering Lecture 7 Designing a Single Cycle Datapath February 18, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 2/19/03 ©UCB Spring 2003 CS152 / Kubiatowicz Lec7.2 Review: Sequential Logic + (Non-)blocking assignments module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ ( posedge CLK) Q <= D; endmodule // FF Good: Doesn’t output until “after edge” Must be careful mixing zero-time blocking assignments and edge-triggering: Probably won’t do what you expect when connecting it to other things! module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ ( posedge CLK) Q = #5 D; endmodule // FF Good: Outputs 5 units “after edge” module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ ( posedge CLK) #5 Q = D; endmodule // FF Probably Not what you Expect: Hold time of 5 units glitches < 5 units ignored 2/19/03 ©UCB Spring 2003 CS152 / Kubiatowicz Lec7.3 Review: MULTIPLY HARDWARE Version 3 ° 32 -bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg ( shift right ), ( 0 -bit Multiplier reg) Product (Multiplier) Multiplicand 32-bit ALU Write Control 32 bits 64 bits Shift Right “HI” “LO” 2/19/03 ©UCB Spring 2003 CS152 / Kubiatowicz Lec7.4 Divide can use almost same hardware (From Book) ° 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, ( 0 -bit Quotient reg) Remainder (Quotient) Divisor 32-bit ALU Write Control 32 bits 64 bits Shift Left “HI” “LO” ° Multiplication and Division can use same hardware!
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2/19/03 ©UCB Spring 2003 CS152 / Kubiatowicz Lec7.5 Review: Booth’s Algorithm Alternate representation Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 000111 10 00 sub (1) 1 1 Middle of run of 1s 00011 11 000 none (0) 0 1 End of run of 1s 00 01 111000 add (1) 0 0 Middle of run of 0s 0 00 1111000 none (0) Examples (8 bits): 0 1 1 1 1 0 beginning of run end of run middle of run 1 8 16 32 1 100 1 001 00010111 23 2 16 0 1 000100 00001110 14 1 2 4 1 1 1 00000 11111101 3 + = = = = + = = 2/19/03 ©UCB Spring 2003 CS152 / Kubiatowicz Lec7.6 MIPS logical instructions ° Instruction Example Meaning Comment ° and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND ° or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR ° xor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XOR ° nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR ° and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant ° or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant ° xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant ° shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant ° shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant ° shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) ° shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable ° shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable ° shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable 2/19/03 ©UCB Spring 2003 CS152 / Kubiatowicz Lec7.7 Shifters Two kinds: logical (RIGHT OR LEFT) -- value shifted in is always "0" arithmetic – (RIGHT ONLY), sign extend msb lsb "0" "0" msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!
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Single-Cycle Processor - CS152 Computer Architecture and...

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