Instruction Decode/Multicycle Processor

Computer Organization and Design: The Hardware/Software Interface

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CS 152 Computer Architecture and Engineering Lecture 8 Single-Cycle (Con’t) Designing a Multicycle Processor February 23, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 2/23/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec8.2 Recap: A Single Cycle Datapath ° Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit ° We have everything except control signals ( underline ) 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux Mux 32 16 imm16 ALUSrc ExtOp MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Equal Instruction<31:0> 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt nPC_sel 2/23/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec8.3 Recap: Flexible Instruction Fetch ° Branch (nPC_sel = “Br”): if (Equal == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 ° Other (nPC_sel = “+4”): PC=PC+4 ° What is encoding of nPC_sel? Direct MUX select? Branch / not branch ° Let’s choose second option nPC_sel Equal MUX 0x 0 10 0 11 1 Adr Inst Memory Adder PC Clk 00 4 nPC_sel imm16 Instruction<31:0> 0 1 Equal nPC_MUX_sel 2/23/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec8.4 Recap: The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = 1 Mux 32 16 imm16 ALUSrc = 0 ExtOp = x MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 Instruction Fetch Unit Clk Equal Instruction<31:0> ° R[rd] <- R[rs] + R[rt] 0 1 0 1 0 1 Imm16 Rd Rs Rt op rs rt rd shamt funct 0 6 11 16 21 26 31 nPC_sel= +4
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2/23/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec8.5 Recap: The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = 0 Extender Mux Mux 32 16 imm16 ALUSrc = 1 ExtOp = 0 MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Equal Instruction<31:0> ° R[rt] <- R[rs] or ZeroExt[Imm16] 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt op rs rt immediate 0 16 21 26 31 nPC_sel= +4 2/23/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec8.6 Recap: The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = 0 Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 Instruction Fetch Unit Clk Equal Instruction<31:0> 0 1 0 1 0 1 Imm16 Rd Rs Rt ° R[rt] <- Data Memory {R[rs] + SignExt[imm16]} op rs rt immediate 0 16 21 26 31 nPC_sel= +4 2/23/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec8.7 Recap: The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = x Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 Instruction Fetch Unit Clk Equal Instruction<31:0> 0 1 0 1 0 1 Imm16 Rd Rs Rt ° Data Memory {R[rs] + SignExt[imm16]} <- R[rt] op rs rt immediate 0 16 21 26 31 nPC_sel= +4 2/23/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec8.8 Recap: The Single Cycle Datapath during Branch 32 ALUctr =Sub Clk busW RegWr = 0 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = x Mux 32 16 imm16 ALUSrc = 0 ExtOp = x
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Instruction Decode/Multicycle Processor - Recap: A Single...

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