Computer Organization and Design: The Hardware/Software Interface

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2/24/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec9.1 Alternative datapath (book): Multiple Cycle Datapath ° Miminizes Hardware: 1 memory, 1 adder Ideal Memory WrAdr Din RAdr 32 32 32 Dout MemWr 32 ALU 32 32 ALUOp ALU Control 32 IRWr Instruction Reg 32 Reg File Ra Rw busW Rb 5 5 32 busA 32 busB RegWr Rs Rt Mux 0 1 Rt Rd PCWr ALUSelA Mux 0 1 RegDst Mux 0 1 32 PC MemtoReg Extend ExtOp Mux 0 1 32 0 1 2 3 4 16 Imm 32 << 2 ALUSelB Mux 1 0 32 Zero Zero PCWrCond PCSrc 32 IorD Mem Data Reg ALU Out B A 2/24/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec9.2 Finite State Machine (FSM) Spec IR <= MEM[PC] PC <= PC + 4 R-type ALUout <= A fun B R[rd] <= ALUout ALUout <= A or ZX R[rt] <= ALUout ORi ALUout <= A + SX R[rt] <= M M <= MEM[ALUout] LW ALUout <= A + SX MEM[ALUout] <= B SW “instruction fetch” “decode” 0000 0001 0100 0101 0110 0111 1000 1001 1010 1011 1100 BEQ 0010 If A = B then PC <= ALUout ALUout <= PC +SX Execute Memory Write-back 2/24/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec9.3 1&2) Start with list of control signals, grouped into fields Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC
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  • Spring '04
  • Kubiatowicz
  • Computer Architecture, Memory Address Register, Central processing unit, CPU cache, operand, memory hierarchy

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