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xceptions (continued), Pipelining

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 10 Exceptions (continued) Introduction to Pipelining March 1, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 3/1/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec10.2 Recap: Microprogramming ° Microprogramming is a fundamental concept implement an instruction set by building a very simple processor and interpreting the instructions essential for very complex instructions and when few register transfers are possible overkill when ISA matches datapath 1-1 sequencer control datapath control micro-PC µ -sequencer: fetch,dispatch, sequential microinstruction ( µ ) Dispatch ROM Opcode µ -Code ROM Decode Decode To DataPath Decoders implement our µ -code language: For instance: rt-ALU rd-ALU mem-ALU 3/1/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec10.3 Recap: Microprogramming ° Microprogramming is a convenient method for implementing structured control state diagrams: Random logic replaced by microPC sequencer and ROM Each line of ROM called a µ instruction: contains sequencer control + values for control points limited state transitions: branch to zero, next sequential, branch to µ instruction address from displatch ROM ° Design of a Microprogramming language 1.Start with list of control signals 2.Group signals together that make sense (vs. random): called “fields” 3.Place fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last) 4.To minimize the width, encode operations that will never be used at the same time 5.Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals 3/1/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec10.4 Recap: Multicycle datapath (book) Ideal Memory WrAdr Din RAdr 32 32 32 Dout MemWr 32 ALU 32 32 ALUOp ALU Control 32 IRWr Instruction Reg 32 Reg File Ra Rw busW Rb 5 5 32 busA 32 busB RegWr Rs Rt Mux 0 1 Rt Rd PCWr ALUSelA Mux 0 1 RegDst Mux 0 1 32 PC MemtoReg Extend ExtOp Mux 0 1 32 0 1 2 3 4 16 Imm 32 << 2 ALUSelB Mux 1 0 32 Zero Zero PCWrCond PCSrc 32 IorD Mem Data Reg ALU Out B A MemRd
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3/1/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec10.5 Recap: Start with List of control signals Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs] RegWrite None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rd MemRead None Memory at address is read, MDR <= Mem[addr] MemWrite None Memory at address is written IorD Memory address = PC Memory address = S IRWrite None IR <= Memory PCWrite None PC <= PCSource PCWriteCond None IF ALUzero then PC <= PCSource PCSource PCSource = ALU PCSource = ALUout ExtOp Zero Extended Sign Extended Single Bit Control Signal name Value Effect ALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code 11 ALU does logical OR ALUSelB 00 2nd ALU input = 4 01 2nd ALU input = Reg[rt] 10 2nd ALU input = extended,shift left 2 11 2nd ALU input = extended Multiple Bit Control 3/1/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec10.6
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xceptions (continued), Pipelining - Recap Microprogramming...

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