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Pipelining (Continued)

Computer Organization and Design: The Hardware/Software Interface

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3/17/03 ©UCB Spring 2003 CS152 / Kubiatowicz Lec13.1 CS152 Computer Architecture and Engineering Lecture 13 Introduction to Pipelining: Datapath and Control March 3 rd , 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 3/3/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec11.2 Recap: Exceptions ° Exception = unprogrammed control transfer system takes action to handle the exception - must record the address of the offending instruction - record any other information necessary to return afterwards returns control to user must save & restore user state ° Allows constuction of a “user virtual machine” normal control flow: sequential, jumps, branches, calls, returns user program System Exception Handler Exception: return from exception 3/3/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec11.3 Recap: Precise Exceptions ° Precise state of the machine is preserved as if program executed up to the offending instruction All previous instructions completed Offending instruction and all following instructions act as if they have not even started Same system code will work on different implementations Position clearly established by IBM Difficult in the presence of pipelining, out-ot-order execution, ... MIPS takes this position ° Imprecise system software has to figure out what is where and put it all back together ° Performance goals often lead designers to forsake precise interrupts system software developers, user, markets etc. usually wish they had not done this ° Modern techniques for out-of-order execution and branch prediction help implement precise interrupts 3/3/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec11.4 Recap: Sequential Laundry ° Sequential laundry takes 6 hours for 4 loads ° If they learned pipelining, how long would laundry take? A B C D 30 40 20 30 40 20 30 40 20 30 40 20 6 PM 7 8 9 10 11 Midnight T a s k O r d e r Time
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3/3/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec11.5 Recap: Pipelining Lessons ° Pipelining doesn’t help latency of single task, it helps throughput of entire workload ° Pipeline rate limited by slowest pipeline stage ° Multiple tasks operating simultaneously using different resources ° Potential speedup = Number pipe stages ° Unbalanced lengths of pipe stages reduces speedup ° Time to “ fill ” pipeline and time to “ drain ” it reduces speedup ° Stall for Dependences A B C D 6 PM 7 8 9 T a s k O r d e r Time 30 40 40 40 40 20 3/3/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec11.6 Recap: Ideal Pipelining IF DCD EX MEM WB IF DCD EX MEM WB IF DCD EX MEM WB IF DCD EX MEM WB IF DCD EX MEM WB Maximum Speedup Number of stages Speedup Time for unpipelined operation Time for longest stage Example: 40ns data path, 5 stages, Longest stage is 10 ns, Speedup 4 Assume instructions are completely independent!
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