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Pipelining Control

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 12 Introduction to Pipelining: Datapath and Control March 8 th , 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 3/8/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec12.2 ° The Five Classic Components of a Computer ° Today’s Topics: Recap last lecture/finish datapath Pipelined Control/ Do it yourself Pipelined Control Administrivia Hazards/Forwarding Exceptions Review MIPS R3000 pipeline The Big Picture: Where are We Now? Control Datapath Memory Processor Input Output 3/8/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec12.3 Can pipelining get us into trouble? ° Yes: Pipeline Hazards structural hazards : attempt to use the same resource two different ways at the same time - E.g., combined washer/dryer would be a structural hazard or folder busy doing something else (watching TV) data hazards : attempt to use item before it is ready - E.g., one sock of pair in dryer and one in washer; can’t fold until get sock from washer through dryer - instruction depends on result of prior instruction still in the pipeline control hazards : attempt to make a decision before condition is evaulated - E.g., washing football uniforms and need to get proper detergent level; need to see after dryer before next load in - branch instructions ° Can always resolve hazards by waiting pipeline control must detect the hazard take action (or delay action) to resolve hazards 3/8/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec12.4 Recap: Data Hazards I-Fet ch DCD MemOpFetch OpFetch Exec Store IFetch DCD ° ° ° Structural Hazard I-Fet ch DCD OpFetch Jump IFetch DCD ° ° ° Control Hazard IF DCD EX Mem WB IF DCD OF Ex Mem RAW (read after write) Data Hazard WAW Data Hazard (write after write) IF DCD OF Ex RS WAR Data Hazard (write after read) IF DCD EX Mem WB IF DCD EX Mem WB
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3/8/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec12.5 Recall: Single cycle control! Data Out Clk 5 Rw Ra Rb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 32 32 32 A B Next Address Control Datapath Control Signals Conditions 3/8/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec12.6 Data Stationary Control ° The Main Control generates the control signals during Reg/Dec Control signals for Exec (ExtOp, ALUSrc, . ..) are used 1 cycle later Control signals for Mem (MemWr Branch) are used 2 cycles later Control signals for Wr (MemtoReg MemWr) are used 3 cycles later IF/ID Register ID/Ex Register Ex/Mem Register Mem/Wr Register Reg/Dec Exec Mem ExtOp ALUOp RegDst ALUSrc Branch MemW r MemtoReg RegWr Main Control ExtOp ALUOp RegDst ALUSrc MemtoReg RegWr MemtoReg RegWr MemtoReg RegWr Branch MemW r Branch MemW r Wr 3/8/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec12.7 Datapath + Data Stationary Control Exec Reg. File Mem Access Data A B S Reg Next PC IR Inst. Mem D Decode Mem Ctrl WB Ctrl M rs rt op rs rt fun im ex me wb rw v me wb rw v wb rw v 3/8/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec12.8 Let’s Try it Out 10 lw
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Pipelining Control - The Big Picture Where are We Now CS152...

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