Static Scheduling and compiler optimizations

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 13 Static Pipeline Scheduling Compiler Optimizations March 15, 2004 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/ 3/15/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec13.2 “Forward” result from one stage to another “or” OK if define read/write properly Recall: Data Hazard Solution: Forwarding I n s t r. O r d e r Time (clock cycles) add r1 ,r2,r3 sub r4, r1 ,r3 and r6, r1 ,r7 or r8, r1 ,r9 xor r10, r1 ,r11 IF ID/RF EX MEM WB ALU Im Reg Dm Reg ALU Im Reg Dm Reg ALU Im Reg Dm Reg Im ALU Reg Dm Reg ALU Im Reg Dm Reg 3/15/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec13.3 Recall: Resolve RAW by “forwarding” (or bypassing) ° Detect nearest valid write op operand register and forward into op latches, bypassing remainder of the pipe Increase muxes to add paths from pipeline registers Data Forwarding = Data Bypassing npc I mem Regs B alu S D mem m IAU PC Regs A im op rw n op rw n op rw n op rw rs rt Forward mux 3/15/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec13.4 FYI: MIPS R3000 clocking discipline ° 2-phase non-overlapping clocks ° Pipeline stage is two (level sensitive) latches phi1 phi2 phi1 phi1 phi2 Edge-triggered
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3/15/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec13.5 MIPS R3000 Instruction Pipeline Inst Fetch Decode Reg. Read ALU / E.A Memory Write Reg TLB I-Cache RF Operation WB E.A. TLB D-Cache TLB I-cache RF ALUALU TLB D-Cache WB Resource Usage Write in phase 1, read in phase 2 => eliminates bypass from WB 3/15/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec13.6 Thus, only 2 levels of forwarding I n s t r. O r d e r Time (clock cycles) add r1 ,r2,r3 sub r4, r1 ,r3 and r6, r1 ,r7 or r8, r1 ,r9 xor r10, r1 ,r11 IF ID/RF EX MEM WB ALU Im Reg Dm Reg ALU Im Reg Dm Reg ALU Im Reg Dm Reg Im ALU Reg Dm Reg ALU Im Reg Dm Reg With MIPS R3000 pipeline, no need to forward from WB stage 3/15/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec13.7 Recall: Examples of stalls/bubbles ° Exceptions: Flush everything above Prevent instructions following exception from commiting state Freeze fetch until exception resolved ° Stalls: Introduce brief stalls into pipeline Decode stage recognizes that current instruction cannot proceed Freeze fetch stage Introduce “bubble” into EX stage (instead of forwarding stalled inst) Can stall until condition is resolved Examples: - mfhi, mflo: need to wait for multiply/divide unit to finish - “Break” instruction for Lab5: stall until release line received - Load delay slot handled this way as well 3/15/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec13.8 Recall: Freeze above & Bubble Below ° Flush accomplished by setting “invalid” bit in pipeline npc I mem Regs B alu S D mem m IAU PC Regs A im op rw n op rw n op rw n op rw rs rt bubble freeze
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3/15/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec13.9 Recall: Achieving Precise Exceptions ° Use pipeline to sort this out!
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