Dynamic Scheduling (Con't), Speculation

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 16 Dynamic Scheduling (Cont), Speculation March 31, 2004 John Kubiatowicz ( ) lecture slides: 3/31/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec16.2 ° The Five Classic Components of a Computer ° Today’s Topics: Recap last lecture Hardware loop unrolling with Tomasulo algorithm Administrivia Speculation, branch prediction Reorder buffers The Big Picture: Where are We Now? Control Datapath Memory Processor Input Output 3/31/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec16.3 Review: Scoreboard Architecture(CDC 6600) Functional Units Registers FP Mult FP Mult FP Divide FP Add Integer Memory SCOREBOARD 3/31/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec16.4 Review: Four Stages of Scoreboard Control ° Issue —decode instructions & check for structural hazards Instructions issued in program order (for hazard checking) Don’t issue if structural hazard Don’t issue if instruction is output dependent on any previously issued but uncompleted instruction (no WAW hazards) ° Read operands —wait until no data hazards, then read operands All real dependencies (RAW hazards) resolved in this stage No forwarding of data in this model! ° Execution —operate on operands (EX) The functional unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. ° Write result —finish execution (WB) Stall until no WAR hazards with previous instructions: Example: DIVD F0,F2,F4 ADDD F10,F0, F8 SUBD F8 ,F8,F14 CDC 6600 scoreboard would stall SUBD until ADDD reads operands
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3/31/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec16.5 Review: Tomasulo Organization FP adders Add1 Add2 Add3 FP multipliers Mult1 Mult2 From Mem FP Registers Reservation Stations Common Data Bus (CDB) To Mem FP Op Queue Load Buffers Store Buffers Load1 Load2 Load3 Load4 Load5 Load6 3/31/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec16.6 Recall: Reservation Station Components Op: Operation to perform in the unit (e.g., + or –) Vj, Vk: Value of Source operands Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) Note: No ready flags as in Scoreboard; Qj,Qk=0 => ready Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register result status (Or “Rename Table”) Mapping from user-visible registers to reservation stations or value 3/31/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec16.7 Recall: Three Stages of Tomasulo Algorithm 1. Issue —get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Execution —operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result —finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available ° Normal data bus: data + destination (“go to” bus) ° Common data bus : data + source
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  • Spring '04
  • Kubiatowicz
  • Computer Architecture, Branch predictor, Tomasulo algorithm, Out-of-order execution, RS Qk, LD MULTD SD, F0 F4 F4

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