Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 17 Branch Prediction, Explicit Renaming, ILP April 5, 2004 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 4/05/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec17.2 Review: Tomasulo Organization FP adders Add1 Add2 Add3 FP multipliers Mult1 Mult2 From Mem FP Registers Reservation Stations Common Data Bus (CDB) To Mem FP Op Queue Load Buffers Store Buffers Load1 Load2 Load3 Load4 Load5 Load6 4/05/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec17.3 Review: Three Stages of Tomasulo Algorithm 1. Issue —get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Execution —operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result —finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available ° Normal data bus: data + destination (“go to” bus) ° Common data bus : data + source (“ come from ” bus) 64 bits of data + 4 bits of Functional Unit source address Write if matches expected Functional Unit (produces result) Does the broadcast 4/05/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec17.4 Review: Tomasulo Architecture ° Reservations stations: renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards of Scoreboard ° Not limited to basic blocks: integer units gets ahead, beyond branches ° Dynamic Scheduling: Scoreboarding/Tomasulo In-order issue, out-of-order execution, out-of-order commit ° Tomasulo can unroll loops dynamically in hardware! Need: renaming (different physical names for different iterations) Fast branch computation
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4/05/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec17.5 3 DIVD ROB2 ,R(F6) 2 ADDD R(F4), ROB1 Review: Tomasulo With Reorder buffer (ROB) To Memory FP adders FP multipliers Reservation Stations FP Op Queue ROB7 ROB6 ROB5 ROB5 ROB3 ROB2 ROB1 -- F0 <val2> <val2> ST 0(R3),F0 ADDD F0,F4,F6 Y Ex F4 M[10] LD F4,0(R3) Y -- BNE F2,<…> N F2 F10 F0 DIVD F2,F10,F6 ADDD F10,F4,F0 LD F0,10(R2) N N N Done? Dest Dest Oldest Newest from Memory 1 10+R2 Dest Reorder Buffer (ROB) Registers 4/05/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec17.6 1. Issue —get instruction from FP Op Queue If reservation station and reorder buffer slot free, issue instr & send operands & reorder buffer no. for destination (this stage sometimes called “dispatch”) 2. Execution —operate on operands (EX) When both operands ready then execute; if not ready, watch CDB for result; when both in reservation station, execute; checks RAW (sometimes called “issue”) 3. Write result —finish execution (WB) Write on Common Data Bus to all awaiting FUs & reorder buffer 4. Commit—update register with reorder buffer (ROB) result When instr. at head of reorder buffer & result present, update register with result (or store to memory) and remove instr from reorder buffer Stores only commit to memory when reach head of ROB
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