Speculation (Finished), Memory Technology

Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 18 Speculation/ILP (Con’t) Locality and Memory Technology April 7, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 4/7/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec18.2 Review: Independent “Fetch” unit Instruction Fetch with Branch Prediction Out-Of-Order Execution Unit Correctness Feedback On Branch Results Stream of Instructions To Execute ° Instruction fetch decoupled from execution ° Often issue logic (+ rename) included with Fetch 4/7/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec18.3 ° Address of branch index to get prediction AND branch address (if taken) Must check for branch match now, since can’t use wrong branch address Grab predicted PC from table since may take several cycles to compute Branch PC Predicted PC =? PC of instruction FETCH Predict taken or untaken Review: Branch Target Buffer (BTB) 4/7/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec18.4 Review: Branch History Table ° BHT is a table of “Predictors” Usually 2-bit, saturating counters Indexed by PC address of Branch – without tags ° Combine Branch Target Buffer and History Tables Branch Target Buffer (BTB): identify branches and hold taken addresses - Trick: identify branch before fetching instruction! - Must be careful not to misidentify branches or destinations Branch History Table makes prediction - Can be complex prediction mechanisms with long history - No address check: Can be good, can be bad (aliasing) T NT T NT T NT NT Predictor 0 Predictor 7 Predictor 1 Branch PC
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4/7/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec18.5 Global Variants for Correllation ° GAs: Global History Register, Per-Address (Set Associative) History Table ° Gshare: Global History Register, Global History Table with Simple attempt at anti-aliasing GAs GBHR PAPHT GShare GPHT GBHR ( n) Address (n) 4/7/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec18.6 Examples: Yeh and Patt classification GBHR GPHT GAg GPHT PABHR PAg PAPHT PABHR PAp ° GAg: Global History Register, Global History Table ° PAg: Per-Address History Register, Global History Table ° PAp: Per-Address History Register, Per-Address History Table 4/7/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec18.7 Can we use explicit register renaming with scoreboard? Functional Units Registers FP Mult FP Mult FP Divide FP Add Integer Integer Memory SCOREBOARD Rename Table 4/7/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec18.8 ° Issue —decode instructions & check for structural hazards & allocate new physical register for result Instructions issued in program order (for hazard checking) Don’t issue if no free physical registers Don’t issue if structural hazard ° Read operands —wait until no hazards, read operands All real dependencies (RAW hazards) resolved in this stage, since we wait for instructions to write back data.
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This note was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at University of California, Berkeley.

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Speculation (Finished), Memory Technology - Review:...

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