Computer Organization and Design: The Hardware/Software Interface

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CS152 Computer Architecture and Engineering Lecture 19 Locality and Memory Technology April 12, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 4/12/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec19.2 Review: Explicit Renaming/Limits to ILP ° Explicit Renaming: more physical registers than ISA. Separates renaming from scheduling - Opens up lots of options for resolving RAW hazards Rename table: tracks current association between architectural registers and physical registers Potentially complicated rename table management ° Multi-issue: simple matter of accounting Must do dataflow analysis across multiple instructions simultaneously Rename table updated as if instructions happened serially! ° To sustain: need execution bandwidth+commit bandwidth To sustain ILP of X need at least - X-way issue, > X execution bandwidth (for mix), X way commit ° Limits to ILP Inherent parallelism of applications as high as 150 IPC Realistic limits rapidly reduce this to < 4 IPC for most applications 4/12/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec19.3 Programs 0 20 40 60 80 100 120 140 160 gcc espresso li fpppp doducd tomcatv 54.8 62.6 17.9 75.2 118.7 150.1 Integer: 18 - 60 FP: 75 - 150 IPC Recall: Upper Limit to ILP: Ideal Machine 4/12/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec19.4 Program 0 10 20 30 40 50 60 gcc espresso li fpppp doducd tomcatv 35 41 16 61 58 60 9 12 10 48 15 6 7 6 46 13 45 6 6 7 45 14 45 2 2 2 29 4 19 46 Change from Infinite window to examine to 2000 and maximum issue of 64 instructions per clock cycle Profile BHT (512) Pick Cor. or BHT Perfect No prediction FP: 15 - 45 Integer: 6 - 12 IPC Recall: More Realistic HW: Branch Impact
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4/12/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec19.5 ° The Five Classic Components of a Computer ° Today’s Topics: Recap last lecture Locality and Memory Hierarchy Administrivia SRAM Memory Technology DRAM Memory Technology Memory Organization The Big Picture: Where are We Now? Control Datapath Memory Processor Input Output 4/12/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec19.6 μProc 60%/yr. (2X/1.5yr) DRAM 9%/yr. (2X/10 yrs) 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance Time “Moore’s Law” Processor-DRAM Memory Gap (latency) Recall: Who Cares About the Memory Hierarchy? “Less’ Law?” 4/12/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec19.7 Recall: Memory Hierarchy of a Modern Computer System ° By taking advantage of the principle of locality: Present the user with as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology. Control Datapath Secondary Storage (Disk) Processor Registers Main Memory (DRAM) Second Level Cache (SRAM) On-Chip Cache 1s 10,000,000s (10s ms) Speed (ns): 10s 100s 100s Gs Size (bytes): Ks Ms Tertiary Storage (Tape) 10,000,000,000s (10s sec) Ts 4/12/04 ©UCB Spring 2004 CS152 / Kubiatowicz Lec19.8 Impact of Memory Hierarchy on Algorithms ° Today CPU time is a function of (ops, cache misses) ° What does this mean to Compilers, Data structures, Algorithms?
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