Computer Organization and Design: The Hardware/Software Interface

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Unformatted text preview: CS152 Computer Architecture and Engineering Lecture 20 Caches April 14, 2003 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs152/ 4/14/04 UCB Spring 2004 CS152 / Kubiatowicz Lec20.2 The Five Classic Components of a Computer Todays Topics: Recap last lecture Simple caching techniques Many ways to improve cache performance Virtual memory? Recap: The Big Picture: Where are We Now? Control Datapath Memory Processor Input Output 4/14/04 UCB Spring 2004 CS152 / Kubiatowicz Lec20.3 Processor $ MEM Memory reference stream <op,addr>, <op,addr>,<op,addr>,<op,addr>, . . . op: i-fetch, read, write Optimize the memory system organization to minimize the average memory access time for typical workloads Workload or Benchmark programs The Art of Memory System Design 4/14/04 UCB Spring 2004 CS152 / Kubiatowicz Lec20.4 Execution_Time = Instruction_Count x Cycle_Time x (ideal CPI + Memory_Stalls/Inst + Other_Stalls/Inst) Memory_Stalls/Inst = Instruction Miss Rate x Instruction Miss Penalty + Loads/Inst x Load Miss Rate x Load Miss Penalty + Stores/Inst x Store Miss Rate x Store Miss Penalty Average Memory Access time (AMAT) = Hit Time L1 + (Miss Rate L1 x Miss Penalty L1 ) = (Hit Rate L1 x Hit Time L1 ) + (Miss Rate L1 x Miss Time L1 ) Recap: Cache Performance 4/14/04 UCB Spring 2004 CS152 / Kubiatowicz Lec20.5 Example: 1 KB Direct Mapped Cache with 32 B Blocks For a 2 ** N byte cache: The uppermost (32 - N) bits are always the Cache Tag The lowest M bits are the Byte Select (Block Size = 2 M ) One cache miss, pull in complete Cache Block (or Cache Line) Cache Index 1 2 3 : Cache Data Byte 0 4 31 : Cache Tag Example: 0x50 Ex: 0x01 0x50 Stored as part of the cache state Valid Bit : 31 Byte 1 Byte 31 : Byte 32 Byte 33 Byte 63 : Byte 992 Byte 1023 : Cache Tag Byte Select Ex: 0x00 9 Block address 4/14/04 UCB Spring 2004 CS152 / Kubiatowicz Lec20.6 Set Associative Cache N-way set associative : N entries for each Cache Index N direct mapped caches operates in parallel Example: Two-way set associative cache Cache Index selects a set from the cache The two tags in the set are compared to the input in parallel Data is selected based on the tag result Cache Data Cache Block 0 Cache Tag Valid : : : Cache Data Cache Block 0 Cache Tag Valid : : : Cache Index Mux 1 Sel1 Sel0 Cache Block Compare Adr Tag Compare OR Hit 4/14/04 UCB Spring 2004 CS152 / Kubiatowicz Lec20.7 Disadvantage of Set Associative Cache N-way Set Associative Cache versus Direct Mapped Cache: N comparators vs. 1 Extra MUX delay for the data Data comes AFTER Hit/Miss decision and set selection In a direct mapped cache, Cache Block is available BEFORE Hit/Miss: Possible to assume a hit and continue. Recover later if miss....
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Caches - CS152 Computer Architecture and Engineering...

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