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Unformatted text preview: BSD Compiler User Guide Version N-2017.09-SP2, December 2017 Copyright Notice and Proprietary Information ©2017 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Trademarks Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at . All other product or company names may be trademarks of their respective owners. Third-Party Links Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practices, availability, and content. Synopsys, Inc. 690 E. Middlefield Road Mountain View, CA 94043 BSD Compiler User Guide, Version N-2017.09-SP2 ii Copyright Notice for the Command-Line Editing Feature © 1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software contributed to Berkeley by Christos Zoulas of Cornell University. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1.Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2.Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3.All advertising materials mentioning features or use of this software must display the following acknowledgement: This product includes software developed by the University of California, Berkeley and its contributors. 4.Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Copyright Notice for the Line-Editing Library © 1992 Simmule Turner and Rich Salz. All rights reserved. This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of the University of California. Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and redistribute it freely, subject to the following restrictions: 1.The authors are not responsible for the consequences of use of this software, no matter how awful, even if they arise from flaws in it. 2.The origin of this software must not be misrepresented, either by explicit claim or by omission. Since few users ever read sources, credits must appear in the documentation. 3.Altered versions must be plainly marked as such, and must not be misrepresented as being the original software. Since few users ever read sources, credits must appear in the documentation. 4.This notice may not be removed or altered. BSD Compiler User Guide, Version N-2017.09-SP2 iii BSD Compiler User Guide, Version N-2017.09-SP2 iv Contents 1. 2. About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Introduction to BSD Compiler BSD Compiler Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Using the BSD Compiler Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Using the BSD Compiler Verification Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the -view Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1-12 Inserting Boundary-Scan Components Design Flow for Inserting Boundary-Scan Components . . . . . . . . . . . . . . . . . . . . . . 2-3 Setting Up the Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Defining the Boundary-Scan Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Predefined Boundary-Scan Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . Identifying Linkage Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identifying Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Custom BSR Segments Pad Cells . . . . . . . . . . . . . . . . . . . . . . . . . . BSR Segment Pad Cell Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Multiple BSR Cells Using the $bsr_segment$ Parameter . . . . . . Netlist and Script Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Integrated Boundary-Scan Functionality . . . . . . . . . . . . . . . . . . . . . 2-5 2-5 2-6 2-6 2-8 2-11 2-20 2-22 2-26 Ordering the Boundary-Scan Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 Setting Boundary-Scan Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 v BSD Compiler User User Guide Guide BSD Compiler N-2017.09-SP2 Version N-2017.09-SP2 Defining IEEE Std 1149.1 Test Access Ports (TAPs) . . . . . . . . . . . . . . . . . . . . . Specifying Hookup Pins for Test Access Ports (TAPs) . . . . . . . . . . . . . . . . Setting Boundary-Scan Test Port Attributes . . . . . . . . . . . . . . . . . . . . . . . . Reporting Boundary-Scan Test Port Attributes . . . . . . . . . . . . . . . . . . . . . . Removing Boundary-Scan Test Port Attributes . . . . . . . . . . . . . . . . . . . . . Selecting the Boundary-Scan Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying a Location for the Boundary-Scan Logic . . . . . . . . . . . . . . . . . . . . . Selecting the TAP Controller Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . Initializing the TAP With Asynchronous Reset Using TRST . . . . . . . . . . . . Initializing the TAP With Asynchronous Reset Using a PUR Cell. . . . . . . . Initializing the TAP With Asynchronous Reset Using PUR and TRST . . . . Initializing the TAP With Synchronous Reset Using TMS. . . . . . . . . . . . . . Configuring the Device Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . USERCODE and Flexible IDCODE Support . . . . . . . . . . . . . . . . . . . . . . . Implementing Standard Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implementing the IEEE Std 1149.1 Instructions . . . . . . . . . . . . . . . . . . . . . Implementing IEEE Std 1149.6-2003 Instructions . . . . . . . . . . . . . . . . . . . Specifying Instruction Opcode Encodings . . . . . . . . . . . . . . . . . . . . . . . . . Writing the STIL Procedure File for Instructions . . . . . . . . . . . . . . . . . . . . . Implementing User-Defined Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining a User-Defined Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . Configuring a Test Data Register Reset Signal . . . . . . . . . . . . . . . . . . . . . Defining a User-Defined Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implementing User Instructions With HIGHZ Behavior. . . . . . . . . . . . . . . . Connecting Design Pins to TAP Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asserting Design Pins By TAP Controller State . . . . . . . . . . . . . . . . . . . . . Asserting Design Pins By Boundary-Scan Instruction . . . . . . . . . . . . . . . . Implementing Scan-Through-TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Scan-Through-TAP Register . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Scan-Through-TAP Instruction . . . . . . . . . . . . . . . . . . . . . . Writing the STIL Procedure File for Scan-Through-TAP. . . . . . . . . . . . . . . Implementing a User Test Data Register Controlled by TAP . . . . . . . . . . . Inserting Scan on Core Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2-30 2-30 2-31 2-31 2-31 2-33 2-34 2-35 2-35 2-38 2-39 2-39 2-40 2-43 2-46 2-48 2-49 2-49 2-50 2-50 2-54 2-55 2-57 2-57 2-58 2-59 2-61 2-62 2-64 2-64 2-64 2-65 Reducing the Number of Control Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65 Implementing the Short BSR Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Associating Short-BSR-Chains With User Instructions . . . . . . . . . . . . . . . . . . . Short BSR Chain Instructions and EXTEST Instructions. . . . . . . . . . . . . . . . . . Conditioning for Excluded BSR Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Previewing Short BSR Chain Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65 2-67 2-69 2-69 2-69 Contents vi BSD Compiler User Guide 3. Version N-2017.09-SP2 Compliance Checking of Short BSR Chain Instructions . . . . . . . . . . . . . . . . . . BSDL Support for Short BSR Chain Instructions. . . . . . . . . . . . . . . . . . . . . . . . BSD Vector Support for Short BSR Chain Instructions . . . . . . . . . . . . . . . . . . . Short BSR Chains Example Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69 2-70 2-70 2-70 Previewing the Boundary-Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71 Generating the Boundary-Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modification of Hierarchical Cells With dont_touch Attribute . . . . . . . . . . . . . . . 2-72 2-75 Writing a Final Gate-Level Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76 Reading the RTL or Gate-Level Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading HDL Source Files With Library Pad Cells. . . . . . . . . . . . . . . . . . . Reading HDL Source Files With Differential I/O Pad Cells. . . . . . . . . . . . . Enabling BSD Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76 2-76 2-78 2-78 2-79 2-80 Specifying Complex Pad Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Test Receivers in a Different Hierarchy . . . . . . . . . . . . . . . . . . . . . . . Specifying Complex Soft Macro Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80 2-87 2-88 Validating Soft-Macro DFT Design Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93 The Boundary-Scan RTL Generation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the RTL Generation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input RTL for the Pad I/O Ring and Core Logic . . . . . . . . . . . . . . . . . . . . . . . . . Representing Core Logic With a Black-Box Module. . . . . . . . . . . . . . . . . . Representing Core Logic With a Full RTL or Netlist Module . . . . . . . . . . . Output RTL for the Boundary-Scan Generated Design . . . . . . . . . . . . . . . . . . . Reading In the Boundary-Scan Design RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying the RTL Boundary-Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL Generation Script Example With Black-Box Core . . . . . . . . . . . . . . . . . . . RTL Generation Script Example With Full RTL Core Model . . . . . . . . . . . . . . . VCS Simulation Script Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95 2-95 2-97 2-98 2-100 2-100 2-100 2-102 2-103 2-103 2-104 2-105 2-105 Inserting Boundary-Scan Components for IEEE Std 1149.6-2003 BSD Compiler Commands and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . link_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 1: Contents Contents 3-3 3-3 vii 1-vii BSD Compiler User User Guide Guide BSD Compiler 4. N-2017.09-SP2 Version N-2017.09-SP2 set_bsd_configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . set_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . set_bsd_ac_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . define_dft_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . set_bsd_instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . set_boundary_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-4 3-4 3-4 3-6 3-7 IEEE Std 1149.6 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 IEEE Std 1149.6 Preview Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 IEEE Std 1149.6 Synthesis Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 BSDL Generation Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 BSD Pattern Generation Specifications for IEEE Std 1149.6 . . . . . . . . . . . . . . . . . . 3-14 Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Example Scripts for an IEEE Std 1149.6 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Verifying the Boundary-Scan Design Design Flow for Verifying a Boundary-Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Preparing for Compliance Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the Netlist for Your Design With Boundary Scan . . . . . . . . . . . . . . . . . Enabling BSD Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying IEEE Std 1149.1 Test Access Ports . . . . . . . . . . . . . . . . . . . . . . . . . . Identifying Test Access Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing Test Access Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identify Linkage Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compliance-Enable Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compliance-Enable Port Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing Definitions of Compliance-Enable Ports . . . . . . . . . . . . . . . . . . 4-3 4-4 4-4 4-4 4-4 4-6 4-6 4-6 4-7 4-8 Checking IEEE Std 1149.1 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the check_bsd Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-9 Resolving Compliance Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Downgrading Errors To Warning Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing to Debug Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Troubleshooting Problems in Your Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Troubleshooting Using preview_dft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Troubleshooting Using insert_dft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4-11 4-14 4-14 4-15 4-15 Contents viii BSD Compiler User Guide 5. Version N-2017.09-SP2 Troubleshooting Using check_bsd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging Your Source File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4-16 Setting Assumed Values on Design Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Generating SDC Constraints for Boundary-Scan Logic . . . . . . . . . . . . . . . . . . . . . . Generating the SDC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Steps for Asynchronous Boundary-Scan Designs . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4-19 4-20 4-21 Generating BSDL and BSD Patterns Creating Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generating Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing STIL and Other Pattern Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initializing Configuration Registers in the Test Program . . . . . . . . . . . . . . . . . . Initializing User-Defined Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . Using a Custom test_setup Initialization Procedure . . . . . . . . . . . . . . . . . . Configuration Registers With Boundary-Scan Reset Connections. . . . . . . Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Providing Additional Settling Time After Update-DR for Slow Pads . . . . . . . . . 5-2 5-2 5-4 5-6 5-6 5-8 5-8 5-9 5-9 Preparing for BSDL Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading the Port-to-Pin Mapping File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Purpose of the Port-to-Pin Mapping File. . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the Port-to-Pin Mapping File . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying the BSD Configuration and Specification . . . . . . . . . . . . . . . . . . . . . . Removing BSD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5-10 5-11 5-12 5-13 5-13 Generat...
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