ee357_hw7_sol

ee357_hw7_sol - EE 357 Homework 7 Spring 09 Redekopp Name:...

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Spring ’0 9 ● Redekopp Name: ___________________________________________ Lec: 9:30 / 11:00 Due: Thurs. April XX in class Score: ________ Note: Attach all work to receive full credit Single-Cycle CPU nd , 3 rd , and 4 th Ed. 1.) (6 pts.) Review your class notes. a. Is it required that the PC is an edge-sensitive register or can it be a level-sensitive latch? Edge-sensitive is required because there is a feedback loop. If level-sensitive we would have a race condition. b. Is it essential or is only desirable to have two READ ports and one WRITE port on the register file? For single-cycle it is necessary because we have to be able to read two operands and write another in the same cycle. c. Is it required that the individual register in the register file are actually edge-sensitive registers or can they be level-sensitive latches? It is necessary for edge-sensitivity because there could be a feedback loop (add $2,$2,$3). 2.) (Exercise 5.2, 3rd Ed.) Describe the effect that a single stuck-at-0 fault (i.e. when the chip is manufactured, that particular signal is always tied to 0 regardless of the intended design) would have for the signal shown below, in the single-cycle datapath (Figure 1) Which instruction, if any, will not work correctly? Place an ‘X’ in the entry in the table for instructions that may not work if the given signal is stuck-at-0. Signal
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ee357_hw7_sol - EE 357 Homework 7 Spring 09 Redekopp Name:...

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