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ee357_hw7 - EE 357 Homework 7 Spring 09 Redekopp Name Lec...

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EE 357 Homework 7 Spring ’0 9 ● Redekopp Name: ___________________________________________ Lec: 9:30 / 11:00 Due: Thurs. April 23 rd before class Score: ________ Submit answers via Blackboard for all problems except 5.) and 6.). For those questions, submit a hardcopy with your answers, diagrams, circuit schematics, etc. Single-Cycle CPU The following exercises are taken from Hennessy and Patterson, CO&D 2 nd , 3 rd , and 4 th Ed. 1.) (6 pts.) Review your class notes. a. Is it required that the PC is an edge-sensitive register or can it be a level-sensitive latch? [ Must be edge-sensitive / Can be level-sensitive ] b. Is it essential or is only desirable to have two READ ports and one WRITE port on the register file? [ Essential / Only Desirable but not essential ] c. Is it required that the individual register in the register file are actually edge-sensitive registers or can they be level-sensitive latches? [ Must be edge-sensitive / Can be level-sensitive ] 2.) (Exercise 5.2, 3rd Ed.) (12 pts.) Describe the effect that a single stuck-at-0 fault (i.e. when the chip is manufactured, that particular signal is always tied to 0 regardless of the intended design) would have for the signal shown below, in the single-cycle datapath (Figure 1) Which instruction, if any, will not work correctly? Place an ‘X’ in the entry in the table for instructions that may not work if the given signal is stuck-at-0. Signal R-Type LW SW BEQ RegWrite ALUop1 ALUop0 Branch MemRead MemWrite 3.) (Exercise 5.3, 3 rd Ed.) (12 pts.) Repeat the previous exercise but now assuming stuck-at- 1 faults.
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