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Unformatted text preview: Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Introduction to SystemVerilog Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Introduction to SystemVerilog Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Introduction to SystemVerilog Copyright © 2003 - 2014 by Doulos. All Rights Reserved All intellectual property rights, including copyright, patents, design rights and know-how in or relating to the course or course materials provided or made available in connection with the course remain the sole property of Doulos Ltd or their respective owners and no copies may be made of course materials unless expressly agreed in writing by Doulos Ltd. All trademarks acknowledged. Doulos takes great care in developing and maintaining materials to ensure they are an effective and accurate medium for communicating design know-how. However, the information provided on a Doulos training course may be out of date or include omissions, inaccuracies or other errors. Except where expressly provided otherwise in agreement between you and Doulos, all information provided directly or indirectly through a Doulos training course is provided “as is” without warranty of any kind. Doulos hereby disclaims all warranties with respect to this information, whether express or implied, including the implied warranties of merchantability, satisfactory quality and fitness for a particular purpose. In no event shall Doulos be liable for any direct, indirect, incidental special or consequential damages, or damages for loss of profits, revenue, data or use, incurred by you or any third party, whether in contract, tort or otherwise, arising for your access to, use of, or reliance upon information obtained from or through a Doulos training course. Doulos reserves the right to make changes, updates or corrections to the information contained in its training courses at any time without notice. Doulos Limited Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Doulos 2055 Gateway Place, Suite 220, San Jose, CA 95110, USA Tel: +44 (0) 1425 471223 Email: [email protected] Tel: 1-888-GO DOULOS Email: [email protected] Introduction to SystemVerilog 1.0 Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Contents 1 Introduction ..................................................................................................3 2 Programming Language Features ................................................................ 13 3 Basic Data Types ......................................................................................... 29 4 Interfaces ..................................................................................................... 43 5 RTL Processes ............................................................................................. 61 6 RTL Types .................................................................................................... 75 7 Clocking Blocks ............................................................................................ 93 8 Arrays and Queues ...................................................................................... 113 9 Bus-Functional Modeling .............................................................................. 127 10 Randomization 11 Coverage ...................................................................................................... 147 12 Other Language Features ............................................................................ 153 13 The Direct Programming Interface ............................................................... 169 14 Index ............................................................................................................ 189 ........................................................................................ 135 Copyright © 2003 - 2014 by Doulos. All Rights Reserved 1 Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. 2 Copyright © 2003 - 2014 by Doulos. All Rights Reserved 1 Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Introduction Aim • To provide some introductory remarks on SystemVerilog and look at the most basic differences compared to Verilog Topics covered • • • • • • What is SystemVerilog? Language evolution Language features Modules, ports, and parameters Standard verification methodologies References Copyright © 2003 - 2014 by Doulos. All Rights Reserved 3 Introduction Introduction to SystemVerilog 1.0 1 Introduction Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. What is SystemVerilog? • The world’s first HDVL, or Hardware Design and Verification Language • IEEE 1800-2009 SystemVerilog is the merger of IEEE Std 1364-2005 Verilog, and IEEE Std 1800-2005 SystemVerilog • SystemVerilog RTL, aka concise RTL • SystemVerilog Assertions, aka SVA • SystemVerilog Test Bench, or class-based verification When it was first introduced, SystemVerilog was announced as the world’s first HDVL, or hardware design and verification language. SystemVerilog is meant to encompass the features of both an HDL, i.e. Verilog, and a language for functional verification. The current version of the SystemVerilog standard resulted from the merger of the IEEE 1364-2005 Verilog standard and the IEEE 1800-2005 SystemVerilog standard. Officially, Verilog no longer exists as a standalone language standard. SystemVerilog is usually viewed as having three main components, namely SystemVerilog RTL, SystemVerilog Assertions, and SystemVerilog Test Bench. Each of these three components go by various names. 4 Copyright © 2003 - 2014 by Doulos. All Rights Reserved 1 Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Language Evolution Classes (from OpenVera) SVA (unified with PSL) DPI (from SuperLog) SystemVerilog 3.0 Interfaces (from SuperLog) VHDL IEEE 1800 SystemVerilog C Verilog 2005 Verilog 1995 SystemVerilog has evolved from the Verilog hardware language. At each stage in the process, new features have been added; Verilog-1995, Verilog-2001 and Verilog-2005 remain as subsets of SystemVerilog. The original Verilog language shares some features with VHDL and C. Verilog-2001 and Verilog-2005 added a few new features to the language, most of which come from VHDL and C. SystemVerilog 3.0 again borrows from VHDL and C – by now most of the features of these languages are part of SystemVerilog – and adds interfaces and assertions. SystemVerilog 3.1/a/1800 add features for writing testbenches, a new syntax for writing assertions and new applications programming interfaces (APIs). Copyright © 2003 - 2014 by Doulos. All Rights Reserved 5 Introduction Introduction to SystemVerilog 1.0 1 Introduction Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. SystemVerilog versus Verilog module blk #(parameter n = 1, m = n) ( input a, b, input [n-1:0] c, d, output [m-1:0] p, output q ); assign ... always ... endmodule Both 4-state scalars Both 4-state vectors module top; 4-state variables logic aa, bb, qq; logic [3:0] cc, dd, pp; blk #(.n(4), .m(4)) inst (.a(aa), .b(bb), .c(cc), .d(dd), .p(pp), .q(qq)); endmodule SystemVerilog uses ANSI-style port, parameter, and argument lists from Verilog 2001 in which both inputs and outputs appear on the same line when declaring modules, tasks, and functions. (Although the legacy Verilog 1995 port syntax still exists for backward compatibility, there are situations in SystemVerilog where ANSI-style port lists must be used.) In Verilog and SystemVerilog, when you insert a range at the front of a comma-separated list of names, you have to be aware that you are in effect introducing a vector data type which is used for all the names in the list. So in the example above, inputs c and d are both n-bit, 4-state vectors. SystemVerilog introduces a new keyword logic that has two different meanings, depending on the context in which it is used. Either it is equivalent to the old keyword reg, meaning that it is defining a 4-state variable as opposed to a wire, or it is used to specific that the data type of a variable or a wire is 4-state, as opposed to something else. Unlike Verilog, where the same 4-state data type is used throughout most of the language, SystemVerilog fully supports named, user-defined data types. Another difference between Verilog and SystemVerilog is that SystemVerilog allows an output port to be connected to a variable: in Verilog, an output port can only be connected to a net/wire. 6 Copyright © 2003 - 2014 by Doulos. All Rights Reserved 1 Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Reg, Logic, and Bit reg 4-state variable logic 4-state type (variable or wire) bit 2-state variable reg [7:0] r; logic [7:0] l; Each bit is 0,1,X, or Z bit [7:0] b; Each bit is 0 or 1 wire [7:0] w; Wires are always 4-state In most situations the new logic keyword is synonymous with reg, but it is also possible to use the logic keyword when declaring wires. However used, logic means that each bit of the variable/wire is 4-state (0, 1, X, or Z). Another new keyword, bit, is used exclusively to define 2-state variables that can have the values 0 and 1. Either of these new types can be used to define vectors (as shown above). Copyright © 2003 - 2014 by Doulos. All Rights Reserved 7 Introduction Introduction to SystemVerilog 1.0 1 Introduction Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Variables, Wires, and Ports module modu ( input wire input var input logic output wire output var output logic ); assign p = b; assign q = c; assign r = a; endmodule a, b, c, p, q, r • A variable can be • • • assigned using procedural assignments or exactly one continuous assignment or connected to exactly one output port No need for wire or var in practice module top; var logic wire logic modu inst1 modu inst2 modu inst3 endmodule a, p, pp, q; b, c, r; (.a, .b, .c, .p, .q, .r); (.*); (.p(pp), .*); Shorthand port connections The keyword var can be used to declare a variable as opposed to a wire. There are almost no situations where the var keyword is actually necessary, so it is usually omitted. The keyword logic used in a port declaration implies that the port is a variable, as opposed to a wire. So in the example above, ports a and p are wires, whereas b, c, q, and r are variables. It very rarely makes and difference whether an input port is a variable or a wire. For many experienced Verilog users, one of the most surprising feature of SystemVerilog is that it allows variables to be used in several contexts where Verilog required the use of a wire. In particular, a SystemVerilog variable can be assigned by exactly one continuous assignment or can be connected to exactly one output port. A variable can still be assigned from any number of procedures, of course. In the example above, we see continuous assignments to variables and wires, and also see output ports connected to variables and wires. In practice, this means that it is very unusual to need to use wires in SystemVerilog: variables are adequate most of the time. Another of SystemVerilog's innovations is shorthand port connections. In the common situation where a port is connected to a variable (or a wire) of the same name, the port connection can be shortened from .name(name) to .name, as shown above. The so-called wildcard port connection .* means connect every port to a variable (or a wire ) of the same name. It is possible to combine a wildcard port connect with explicit connections so that certain ports are connected explicitly by-name and others are connected using the wildcard connection. 8 Copyright © 2003 - 2014 by Doulos. All Rights Reserved 1 Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. SystemVerilog Language Features C-style data types & control - enum, struct, typedef, ++, break, return Synthesis-friendly "concise" RTL notation Packages Interfaces SystemVerilog Assertions Clocking blocks (synchronization between DUT and test bench) Object-oriented programming - classes Constrained random stimulus generation Functional coverage Dynamic processes, dynamic arrays, queues, mailboxes, semaphores Direct Programming Interface (DPI) - calling C from SystemVerilog Extensions to VPI SystemVerilog offers three distinct capabilities, sometimes referred to as SystemVerilog RTL, SystemVerilog Assertions, and SystemVerilog Test Bench. SystemVerilog RTL, of course, is for hardware design, and you can think of it as a series of improvements to Verilog, which include programming language features from C, interfaces, and packages as well as the RTL constructs. SystemVerilog Assertions are for writing checkers, and SystemVerilog Test Bench is for creating constrained random verification environments, which is perhaps the most significant application of SystemVerilog today. Copyright © 2003 - 2014 by Doulos. All Rights Reserved 9 Introduction Introduction to SystemVerilog 1.0 1 Introduction Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Caveats • • • • • • • • • C-like control constructs and data types Concise RTL A better Verilog VHDL-like package and import Assertions Non-portable constructs Ill-defined Classes Constraints and coverage based on classes Built-in types - strings, queues, maps Class-based verification Virtual interfaces Used by standard verification methodologies SystemVerilog is a very large and complex language, and as we have already seen could be regarded as being several different languages rolled into one. As a result, simulator vendors have struggled over the years to implement the entire language in a consistent and high quality way, and it is very important to be aware of some of the pitfalls as you start to adopt SystemVerilog. Otherwise you will waste a lot of time trying to debug your "unusual" coding style or have difficulties porting code between simulators. There are some areas of SystemVerilog that are pretty solid, that is, well-defined and consistently implemented. These include the features that are close to the original Verilog language or close to VHDL or C, and include the new synthesis-aware RTL features and assertions (SVA). The class-based features are also well-defined and well-implemented, mainly due to their prevalence in the standard verification methodologies (VMM, OVM, and UVM). 10 Copyright © 2003 - 2014 by Doulos. All Rights Reserved 1 Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. The UVM Family Tree Cadence Mentor Synopsys Vera e eRM RVM SV/e SV/SC URM AVM SV VMM SV OVM OVM 2.1.1 Accellera SV UVM The diagram above shows the "family tree" of functional verification methodologies related to OVM and UVM. The headings Cadence/Mentor/Synopsys indicates the vendor from which each of the lineages originated. The superscripts show the principle language of each methodology. The meaning of each abbreviation is as follows: • AVM – Advanced Verification Methodology • eRM – e Reuse Methodology • OVM – Open Verification Methodology • RVM – Reference Verification Methodology • URM – Universal Reuse Methodology • UVM – Universal Verification Methodology • VMM – Verification Methodology Manual Copyright © 2003 - 2014 by Doulos. All Rights Reserved 11 Introduction Introduction to SystemVerilog 1.0 1 Introduction Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Books and Resources • Google and Amazon • • Search for systemverilog • Search for systemverilog 1800-2012 • • End A number of SystemVerilog resources are variable, including manuals, books and web sites. The SystemVerilog LRM is available to download, free of charge, from the IEEE. For information on a particular tool’s SystemVerilog support, refer to the tool’s documentation, which may include User Guides, Release Notes and Application Notes. A number of books about SystemVerilog have been published. These cover the full range of the application of SystemVerilog. You can find details of these on the Internet. Details of the Doulos Golden Reference Guides mentioned are as follows: SystemVerilog Golden Reference Guide; 410 pages, Doulos Ltd., ISBN 0-9547345-3-X SystemVerilog Assertions Golden Reference Guide; 102 pages, Doulos Ltd., ISBN 0-9547345-4-8 . 12 Copyright © 2003 - 2014 by Doulos. All Rights Reserved Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Introduction to SystemVerilog 1.0 Programming Language Features Programming Language Features Aim • To learn SystemVerilog’s improved programming language features, many inspired by C Topics covered • • • • • • • Static and automatic variables Increment and assignment operators Labelling blocks Time units Do While and Assert Task and function syntax Strings and $sformat Copyright © 2003 - 2014 by Doulos. All Rights Reserved 2 13 Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Programming Language Features 2 C-Like Language Features logic [7:0] a, b, f; always_comb Combinational process (always_ff = clocked process) begin static int count = 8; for (int i = 0; i < 8; i++) Local variable declarations Variable initialization begin count--; if (a[i]) continue; int = 32 bits, no Xs or Zs ++ -- if (b[i]) break; end break, continue f = count; end SystemVerilog adds several features directly inspired by the C language. SystemVerilog permits local declarations inside blocks (begin-end or fork-join) without any need to name those blocks. It also permits local declarations within the first line of a for loop, as shown above. SystemVerilog supports proper variable initialization. That is, the initial value given to the variable will be the value of the variable the first time it is read: unlike Verilog, SystemVerilog does not rely on implicit initial statements to initialize variables. SystemVerilog adds several so-called 2-state data types such as int, called 2-state because each individual bit is either 0 or 1 (no Xs or Zs). Type int is 32 bits and signed. SystemVerilog adds ++, == and all the assignment operators from C. Assignment operators modify the value of the variable on the left-hand-side. SystemVerilog adds the keywords break and continue from C. break jumps out of the enclosing loop, continue jumps to the next iteration of the enclosing loop. 14 Copyright © 2003 - 2014 by Doulos. All Rights Reserved Restricted document for designated employees of Nvidia Corporation. Provided for Nvidia on 17-May-2019. Introduction to SystemVerilog 1.0 Programming Language Features Static vs Automatic Variables always_comb begin static int count = 8; Initialized once at compile time ... always_comb begin automatic int count = 8; Initialized each time around ... always_comb begin int count; static, but no initialization count = 8; Variables that are declared locally and initialized inline may be declared as static or automatic. static variables are only initialized once and retain their values on exit from the block. automatic variables are re-initialized each time the block is entered. It is an error to omit the keyword static i...
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