dftxg1.pdf - DFT Compiler Scan User Guide Version G-2012.06-SP2 September 2012 Copyright Notice and Proprietary Information Copyright \u00a9 2012 Synopsys

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Unformatted text preview: DFT Compiler Scan User Guide Version G-2012.06-SP2, September 2012 Copyright Notice and Proprietary Information Copyright © 2012 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader s responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Registered Trademarks (®) Synopsys, AEON, AMPS, ARC, ARC logo, Architecture to Production, Astro, Behavior Extracting Synthesis Technology BOCP, Cadabra, CATS, Certify, CHIPit, CODE V, CoMET, Confirma, Design Compiler, DesignSphere, DesignWare, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HAPS logo, HapsTrak, HDL Analyst, HSIM, HSPICE, Identify, IP Catalyst, IP Producer, Leda, LightTools, Magma, Magma Design Automation, Magma logo, MAST, MaVeric, MdeMon logo, MegaLab, METeor, mGoods logo, MIIX logo, ModelTools, Molten, NanoSim, NOVeA, OpenVera, Optimization Environment, ORA, PathMill, Physical Compiler, PrimeTime, QuickCap, SCOPE, SiliconSmart, SIMAID, Simply Better Synthesis, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, SVP Café, Syndicated, Synopsys DesignWare, Synopsys VCS, Synplicity, Synplicity logo, Synplify, Synplify Lite, Synplify Pro, Synthesis Constraints, Talus, TetraMAX, TimeMill, UMRBus, VCS, Vera, YieldExplorer, and ZMATRIX are registered trademarks of Synopsys, Inc. Trademarks (™) AFGen, Apollo, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, Custom WaveView, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision, DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Encore, EPIC, Galaxy, HANEX, HDL Compiler, Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping plus System, HSIM , i-Virtual Stepper, IC Compiler, IICE, in-Sync, iN-Tandem, Intelli, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-PL, Platform Architect, Polaris, Power Compiler, Processor Designer, Raphael, RippledMixer, Saturn, Scirocco, Scirocco-i, SiWare, SPW, Star-RCXT, Star-SimXT, StarRC, Synphony Model System Compiler, System Compiler, System Designer, System Studio, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, Virtualizer, VMC, and Worksheet Buffer are trademarks of Synopsys, Inc. Service Marks (SM) MAP-in and TAP-in are service marks of Synopsys, Inc. Third Party Trademark Acknowledgements SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. Entrust is a registered trademark of Entrust Inc. in the United States and in certain other countries. In Canada, Entrust is a trademark or registered trademark of Entrust Technologies Limited. Used by Entrust.net Inc. under license. All other product or company names may be trademarks of their respective owners. Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA 94043 DFT Compiler Scan User Guide, version G-2012.06-SP2 ii Copyright Statement for the Command-Line Editing Feature Copyright © 1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software contributed to Berkeley by Christos Zoulas of Cornell University. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. All advertising materials mentioning features or use of this software must display the following acknowledgement: This product includes software developed by the University of California, Berkeley and its contributors. 4. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Copyright Statement for the Line-Editing Library Copyright © 1992 Simmule Turner and Rich Salz. All rights reserved. This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of the University of California. Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and redistribute it freely, subject to the following restrictions: 1. The authors are not responsible for the consequences of use of this software, no matter how awful, even if they arise from flaws in it. 2. The origin of this software must not be misrepresented, either by explicit claim or by omission. Since few users ever read sources, credits must appear in the documentation. 3. Altered versions must be plainly marked as such, and must not be misrepresented as being the original software. Since few users ever read sources, credits must appear in the documentation. 4. This notice may not be removed or altered. DFT Compiler Scan User Guide, version G-2012.06-SP2 iii DFT Compiler Scan User Guide, version G-2012.06-SP2 iv Contents 1. About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv Key Design-for-Test Flows and Methodologies Design-for-Test Flows in the Logic Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unmapped Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizing Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Postprocessing Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Building Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mapped Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading In Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Scan Replacement and Building Scan Chains. . . . . . . . . . . . . Mapped Designs With Existing Scan Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading In Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking Test Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Designing Block by Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controlling Scan Replacement During Scan Insertion . . . . . . . . . . . . . . . . . . . 1-2 1-2 1-4 1-5 1-6 1-7 1-10 1-11 1-13 1-15 1-16 1-17 1-17 Hierarchical Scan Synthesis Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to Test Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linking Test Models to Library Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking Library Cells for CTL Model Information . . . . . . . . . . . . . . . . . . . . . . Scan Assembly Using Test Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving Test Models for Subdesigns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Test Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading Designs Into TetraMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1-19 1-23 1-24 1-24 1-25 1-26 1-28 v DFT DFT Compiler Compiler Scan Scan User User Guide Guide G-2012.06-SP2 Version G-2012.06-SP2 Managing Test Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top-Level Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hierarchical ScanEnable Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 1-30 1-32 DFT Flows in Design Compiler Topographical Mode . . . . . . . . . . . . . . . . . . . . . . . . Supported DFT Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFT Insertion in Design Compiler Topographical Mode . . . . . . . . . . . . . . . . . . Hierarchical Support in Design Compiler Topographical Mode . . . . . . . . . . . . . Top-Level Design Stitching Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing a Bottom-up or Hierarchical Compile . . . . . . . . . . . . . . . . . . . . 1-33 1-34 1-34 1-36 1-36 1-38 Scan Insertion Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom-Up Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top-Down Scan Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 1-42 1-44 DFT Compiler Default Scan Synthesis Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Element Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Area and Timing Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45 1-46 1-46 1-47 1-47 1-47 Getting the Best Results With Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48 DFT Compiler and Power Compiler Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . Improving Testability in Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inserting Control Points in Control Clock Gating . . . . . . . . . . . . . . . . . . . . Scan-Enable Signal Versus Test-Mode Signal . . . . . . . . . . . . . . . . . . . . . . Inserting Observation Points to Control Clock Gating . . . . . . . . . . . . . . . . Choosing a Depth for Observability Logic . . . . . . . . . . . . . . . . . . . . . . . . . Power Compiler/DFT Compiler Interoperability Flows . . . . . . . . . . . . . . . . . . . Using Test-Mode Signals With Power Compiler . . . . . . . . . . . . . . . . . . . . . Using Scan-Enable Signals With Power Compiler . . . . . . . . . . . . . . . . . . . Connecting Test Pins to Clock-Gating Cells Using the insert_dft Command. . . Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hookup Testport Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Rule Checking Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Signals for Automatic Clock-Gating Cell Test Pin Connections . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 1-49 1-50 1-51 1-53 1-55 1-55 1-55 1-56 1-59 1-60 1-61 1-61 1-62 1-64 Contents vi DFT Compiler Scan User Guide 2. 3. Version G-2012.06-SP2 Running RTL Test Design Rule Checking Understanding the Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Specifying Setup Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Generating a Test Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining a Test Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading in an Initialization Protocol in STIL Format. . . . . . . . . . . . . . . . . . Setting the Scan Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Protocol Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Protocol Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-3 2-4 2-7 2-8 2-8 2-9 Running RTL Test DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Understanding the Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Violations That Prevent Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncontrollable Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Control Pins in Active State . . . . . . . . . . . . . . . . . . . . . . . . Violations That Prevent Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Used As Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Black Box Feeds Into Clock or Asynchronous Control . . . . . . . . . . . . . . . . Source Register Launch Before Destination Register Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registered Clock-Gating Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Contention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Feeding Multiple Register Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . Violations That Reduce Fault Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combinational Feedback Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks That Interact With Register Input . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Clocks That Feed Into Latches and Flip-Flops . . . . . . . . . . . . . . . Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-13 2-13 2-14 2-14 2-15 2-15 2-16 2-17 2-17 2-18 2-18 2-19 2-19 2-20 2-21 Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Running the Test DRC Debugger Starting and Exiting the Graphical User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Exploring the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Hierarchy View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-4 3-4 3-4 Chapter 1: Contents Contents 1-vii vii DFT DFT Compiler Compiler Scan Scan User User Guide Guide 4. G-2012.06-SP2 Version G-2012.06-SP2 Viewing Man Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking Scan Test Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examining DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Test Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-5 3-5 3-6 3-6 Viewing Design Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examining DRC Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inspecting DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inspecting Static DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inspecting Dynamic DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-6 3-8 3-8 3-14 Commands Specific to the DFT Tools in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . gui_inspect_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gui_wave_add_signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gui_violation_schematic_add_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-17 3-18 3-18 Performing Scan Replacement Scan Replacement Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Preparing for Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting a Scan Replacement Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identifying Barriers to Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technology Library Does Not Contain Appropriate Scan Cells . . . . . . . . . Support for Different Types of Sequential Cells and Violations . . . . . . . . . Attributes That Prevent Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . Invalid Clock Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invalid Asynchronous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preventing Scan Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-4 4-6 4-6 4-7 4-8 4-9 4-11 4-12 Specifying a Scan Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Types of Scan Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Flip-Flop Scan Style. . . . . . . . . . . . . . . . . ....
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